From patchwork Fri Feb 5 13:42:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8234861 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0B066BEEE5 for ; Fri, 5 Feb 2016 14:04:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 10E9F201CD for ; Fri, 5 Feb 2016 14:04:58 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CC5520390 for ; Fri, 5 Feb 2016 14:04:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRgxl-0000Vd-L6; Fri, 05 Feb 2016 14:02:17 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRgxg-0000Bw-Hw for xen-devel@lists.xen.org; Fri, 05 Feb 2016 14:02:12 +0000 Received: from [85.158.139.211] by server-11.bemta-5.messagelabs.com id 45/05-25857-46BA4B65; Fri, 05 Feb 2016 14:02:12 +0000 X-Env-Sender: prvs=8364524b4=Andrew.Cooper3@citrix.com X-Msg-Ref: server-6.tower-206.messagelabs.com!1454680924!20279727!5 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 58549 invoked from network); 5 Feb 2016 14:02:11 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-6.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 5 Feb 2016 14:02:11 -0000 X-IronPort-AV: E=Sophos;i="5.22,400,1449532800"; d="scan'208";a="336333927" From: Andrew Cooper To: Xen-devel Date: Fri, 5 Feb 2016 13:42:10 +0000 Message-ID: <1454679743-18133-18-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> References: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v2 17/30] x86/cpu: Common infrastructure for levelling context switching X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change is purely scaffolding to reduce the complexity of the following three patches. Signed-off-by: Andrew Cooper --- CC: Jan Beulich v2: s/cpumasks/cpuidmasks/ --- xen/arch/x86/cpu/common.c | 6 ++++++ xen/include/asm-x86/cpufeature.h | 1 + xen/include/asm-x86/processor.h | 28 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 46d93a6..3fdae96 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -36,6 +36,12 @@ integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx); unsigned int opt_cpuid_mask_ext_edx = ~0u; integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx); +unsigned int __initdata expected_levelling_cap; +unsigned int __read_mostly levelling_caps; + +DEFINE_PER_CPU(struct cpuidmasks, cpuidmasks); +struct cpuidmasks __read_mostly cpuidmask_defaults; + const struct cpu_dev *__read_mostly cpu_devs[X86_VENDOR_NUM] = {}; unsigned int paddr_bits __read_mostly = 36; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index f228fa2..8ac6b56 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -95,6 +95,7 @@ #define cpu_has_xsavec boot_cpu_has(X86_FEATURE_XSAVEC) #define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1) #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) +#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) enum _cache_type { CACHE_TYPE_NULL = 0, diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h index 271340e..09e82d8 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -574,6 +574,34 @@ void microcode_set_module(unsigned int); int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void), unsigned long len); int microcode_resume_cpu(unsigned int cpu); +#define LCAP_faulting (1U << 0) +#define LCAP_1cd (3U << 1) +#define LCAP_e1cd (3U << 3) +#define LCAP_Da1 (1U << 5) +#define LCAP_6c (1U << 6) +#define LCAP_7ab0 (3U << 7) + +/* + * Expected levelling capabilities (given cpuid vendor/family information), + * and levelling capabilities actually available (given MSR probing). + */ +extern unsigned int expected_levelling_cap, levelling_caps; + +struct cpuidmasks +{ + uint64_t _1cd; + uint64_t e1cd; + uint64_t Da1; + uint64_t _6c; + uint64_t _7ab0; +}; + +/* Per CPU shadows of masking MSR values, for lazy context switching. */ +DECLARE_PER_CPU(struct cpuidmasks, cpuidmasks); + +/* Default masking MSR values, calculated at boot. */ +extern struct cpuidmasks cpuidmask_defaults; + enum get_cpu_vendor { gcv_host_early, gcv_host_late,