From patchwork Fri Feb 5 13:42:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8234381 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4A733BEEE5 for ; Fri, 5 Feb 2016 13:44:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 49CD120389 for ; Fri, 5 Feb 2016 13:44:43 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 442FA20383 for ; Fri, 5 Feb 2016 13:44:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRgef-0006jv-Kc; Fri, 05 Feb 2016 13:42:33 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aRged-0006hw-9U for xen-devel@lists.xen.org; Fri, 05 Feb 2016 13:42:31 +0000 Received: from [85.158.139.211] by server-16.bemta-5.messagelabs.com id 84/C5-13828-6C6A4B65; Fri, 05 Feb 2016 13:42:30 +0000 X-Env-Sender: prvs=8364524b4=Andrew.Cooper3@citrix.com X-Msg-Ref: server-10.tower-206.messagelabs.com!1454679746!20544217!3 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 29365 invoked from network); 5 Feb 2016 13:42:29 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-10.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 5 Feb 2016 13:42:29 -0000 X-IronPort-AV: E=Sophos;i="5.22,400,1449532800"; d="scan'208";a="329916715" From: Andrew Cooper To: Xen-devel Date: Fri, 5 Feb 2016 13:42:00 +0000 Message-ID: <1454679743-18133-8-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> References: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v2 07/30] xen/x86: Collect more cpuid feature leaves X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP New words are: * 0x80000007.edx - Contains Invarient TSC * 0x80000008.ebx - Newly used for AMD Zen processors In addition, replace some open-coded ITSC and EFRO manipulation. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich v2: * Rely on ordering of generic_identify() to simplify init_amd() * Remove opencoded EFRO manipulation as well --- xen/arch/x86/cpu/amd.c | 21 +++------------------ xen/arch/x86/cpu/common.c | 6 ++++++ xen/arch/x86/cpu/intel.c | 2 +- xen/arch/x86/domain.c | 2 +- 4 files changed, 11 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index c184f57..f9dc532 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -294,21 +294,6 @@ int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...) return 0; } -/* Can this system suffer from TSC drift due to C1 clock ramping? */ -static int c1_ramping_may_cause_clock_drift(struct cpuinfo_x86 *c) -{ - if (cpuid_edx(0x80000007) & (1<<8)) { - /* - * CPUID.AdvPowerMgmtInfo.TscInvariant - * EDX bit 8, 8000_0007 - * Invariant TSC on 8th Gen or newer, use it - * (assume all cores have invariant TSC) - */ - return 0; - } - return 1; -} - /* * Disable C1-Clock ramping if enabled in PMM7.CpuLowPwrEnh on 8th-generation * cores only. Assume BIOS has setup all Northbridges equivalently. @@ -475,7 +460,7 @@ static void init_amd(struct cpuinfo_x86 *c) } if (c->extended_cpuid_level >= 0x80000007) { - if (cpuid_edx(0x80000007) & (1<<8)) { + if (cpu_has(c, X86_FEATURE_ITSC)) { __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); if (c->x86 != 0x11) @@ -600,14 +585,14 @@ static void init_amd(struct cpuinfo_x86 *c) wrmsrl(MSR_K7_PERFCTR3, 0); } - if (cpuid_edx(0x80000007) & (1 << 10)) { + if (cpu_has(c, X86_FEATURE_EFRO)) { rdmsr(MSR_K7_HWCR, l, h); l |= (1 << 27); /* Enable read-only APERF/MPERF bit */ wrmsr(MSR_K7_HWCR, l, h); } /* Prevent TSC drift in non single-processor, single-core platforms. */ - if ((smp_processor_id() == 1) && c1_ramping_may_cause_clock_drift(c)) + if ((smp_processor_id() == 1) && !cpu_has(c, X86_FEATURE_ITSC)) disable_c1_ramping(); set_cpuidmask(c); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 335f044..a99cc7c 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -269,6 +269,12 @@ static void generic_identify(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >= 0x80000004) get_model_name(c); /* Default name */ + if (c->extended_cpuid_level >= 0x80000007) + c->x86_capability[cpufeat_word(X86_FEATURE_ITSC)] + = cpuid_edx(0x80000007); + if (c->extended_cpuid_level >= 0x80000008) + c->x86_capability[cpufeat_word(X86_FEATURE_CLZERO)] + = cpuid_ebx(0x80000008); /* Intel-defined flags: level 0x00000007 */ if ( c->cpuid_level >= 0x00000007 ) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index d4f574b..bdf89f6 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -281,7 +281,7 @@ static void init_intel(struct cpuinfo_x86 *c) if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); - if (cpuid_edx(0x80000007) & (1u<<8)) { + if (cpu_has(c, X86_FEATURE_ITSC)) { __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 9d43f7b..8f2c0b6 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -2605,7 +2605,7 @@ void domain_cpuid( */ if ( (input == 0x80000007) && /* Advanced Power Management */ !d->disable_migrate && !d->arch.vtsc ) - *edx &= ~(1u<<8); /* TSC Invariant */ + *edx &= ~cpufeat_mask(X86_FEATURE_ITSC); return; }