From patchwork Tue Mar 15 15:35:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8589831 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8662F9F294 for ; Tue, 15 Mar 2016 15:38:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 488542021F for ; Tue, 15 Mar 2016 15:38:15 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E2182024C for ; Tue, 15 Mar 2016 15:38:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1afr0P-0001MQ-4k; Tue, 15 Mar 2016 15:35:33 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1afr0N-0001La-3N for xen-devel@lists.xen.org; Tue, 15 Mar 2016 15:35:31 +0000 Received: from [85.158.139.211] by server-12.bemta-5.messagelabs.com id 9A/41-16378-2CB28E65; Tue, 15 Mar 2016 15:35:30 +0000 X-Env-Sender: prvs=87506bf53=Andrew.Cooper3@citrix.com X-Msg-Ref: server-2.tower-206.messagelabs.com!1458056127!13093614!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 43765 invoked from network); 15 Mar 2016 15:35:29 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-2.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 15 Mar 2016 15:35:29 -0000 X-IronPort-AV: E=Sophos;i="5.24,339,1454976000"; d="scan'208";a="339075352" From: Andrew Cooper To: Xen-devel Date: Tue, 15 Mar 2016 15:35:03 +0000 Message-ID: <1458056124-8024-8-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458056124-8024-1-git-send-email-andrew.cooper3@citrix.com> References: <1458056124-8024-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v3 07/28] xen/x86: Annotate special features X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some bits in a featureset are not simple a indication of new functionality, and require special handling. APIC, OSXSAVE and OSPKE are fast-forwards of other pieces of state; IA32_APIC_BASE.EN, CR4.OSXSAVE and CR4.OSPKE. Xen will take care of filling these appropriately at runtime. FDP_EXCP_ONLY and NO_FPU_SEL are bits indicating reduced functionality in the x87 pipeline. The effects of these cannot be hidden from the guest, so the host values will always be provided. HTT and CMP_LEGACY indicate how to interpret other cpuid leaves. In most cases, the toolstack value will be used (with the expectation that these flags will match the other provided topology information). However with cpuid masking, the host values are presented as masking cannot influence what the guest sees in the dependent leaves. Signed-off-by: Andrew Cooper Reviewed-by: Konrad Rzeszutek Wilk Acked-by: Jan Beulich --- CC: Jan Beulich Essentially new in v3. Replaces "Store antifeatures inverted in a featureset" --- xen/arch/x86/cpuid.c | 2 ++ xen/include/asm-x86/cpuid.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 26 +++++++++++++++++++------- xen/tools/gen-cpuid.py | 17 ++++++++++++++++- 4 files changed, 38 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 05cd646..77e008a 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -3,10 +3,12 @@ #include const uint32_t known_features[] = INIT_KNOWN_FEATURES; +const uint32_t special_features[] = INIT_SPECIAL_FEATURES; static void __init __maybe_unused build_assertions(void) { BUILD_BUG_ON(ARRAY_SIZE(known_features) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(special_features) != FSCAPINTS); } /* diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h index b72d88f..0ecf357 100644 --- a/xen/include/asm-x86/cpuid.h +++ b/xen/include/asm-x86/cpuid.h @@ -10,6 +10,7 @@ #include extern const uint32_t known_features[FSCAPINTS]; +extern const uint32_t special_features[FSCAPINTS]; #endif /* __ASSEMBLY__ */ #endif /* !__X86_CPUID_H__ */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 219ff1c..9389ed9 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -81,6 +81,18 @@ enum { * CPUID instruction, but this is not preclude other sources of information. */ +/* + * Attribute syntax: + * + * Attributes for a particular feature are provided as characters before the + * first space in the comment immediately following the feature value. + * + * Special: '!' + * This bit has special properties and is not a straight indication of a + * piece of new functionality. Xen will handle these differently, + * and may override toolstack settings completely. + */ + /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ XEN_CPUFEATURE(FPU, 0*32+ 0) /* Onboard FPU */ XEN_CPUFEATURE(VME, 0*32+ 1) /* Virtual Mode Extensions */ @@ -91,7 +103,7 @@ XEN_CPUFEATURE(MSR, 0*32+ 5) /* Model-Specific Registers, RDMSR, WRM XEN_CPUFEATURE(PAE, 0*32+ 6) /* Physical Address Extensions */ XEN_CPUFEATURE(MCE, 0*32+ 7) /* Machine Check Architecture */ XEN_CPUFEATURE(CX8, 0*32+ 8) /* CMPXCHG8 instruction */ -XEN_CPUFEATURE(APIC, 0*32+ 9) /* Onboard APIC */ +XEN_CPUFEATURE(APIC, 0*32+ 9) /*! Onboard APIC */ XEN_CPUFEATURE(SEP, 0*32+11) /* SYSENTER/SYSEXIT */ XEN_CPUFEATURE(MTRR, 0*32+12) /* Memory Type Range Registers */ XEN_CPUFEATURE(PGE, 0*32+13) /* Page Global Enable */ @@ -106,7 +118,7 @@ XEN_CPUFEATURE(MMX, 0*32+23) /* Multimedia Extensions */ XEN_CPUFEATURE(FXSR, 0*32+24) /* FXSAVE and FXRSTOR instructions */ XEN_CPUFEATURE(SSE, 0*32+25) /* Streaming SIMD Extensions */ XEN_CPUFEATURE(SSE2, 0*32+26) /* Streaming SIMD Extensions-2 */ -XEN_CPUFEATURE(HTT, 0*32+28) /* Hyper-Threading Technology */ +XEN_CPUFEATURE(HTT, 0*32+28) /*! Hyper-Threading Technology */ XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ @@ -135,7 +147,7 @@ XEN_CPUFEATURE(POPCNT, 1*32+23) /* POPCNT instruction */ XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /* TSC Deadline Timer */ XEN_CPUFEATURE(AESNI, 1*32+25) /* AES instructions */ XEN_CPUFEATURE(XSAVE, 1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ -XEN_CPUFEATURE(OSXSAVE, 1*32+27) /* OSXSAVE */ +XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ XEN_CPUFEATURE(AVX, 1*32+28) /* Advanced Vector Extensions */ XEN_CPUFEATURE(F16C, 1*32+29) /* Half-precision convert instruction */ XEN_CPUFEATURE(RDRAND, 1*32+30) /* Digital Random Number Generator */ @@ -154,7 +166,7 @@ XEN_CPUFEATURE(3DNOW, 2*32+31) /* 3DNow! */ /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /* LAHF/SAHF in long mode */ -XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /* If yes HyperThreading not valid */ +XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*! If yes HyperThreading not valid */ XEN_CPUFEATURE(SVM, 3*32+ 2) /* Secure virtual machine */ XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /* CR8 in 32-bit mode */ @@ -187,14 +199,14 @@ XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /* TSC_ADJUST MSR available */ XEN_CPUFEATURE(BMI1, 5*32+ 3) /* 1st bit manipulation extensions */ XEN_CPUFEATURE(HLE, 5*32+ 4) /* Hardware Lock Elision */ XEN_CPUFEATURE(AVX2, 5*32+ 5) /* AVX2 instructions */ -XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /* x87 FDP only updated on exception. */ +XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ XEN_CPUFEATURE(SMEP, 5*32+ 7) /* Supervisor Mode Execution Protection */ XEN_CPUFEATURE(BMI2, 5*32+ 8) /* 2nd bit manipulation extensions */ XEN_CPUFEATURE(ERMS, 5*32+ 9) /* Enhanced REP MOVSB/STOSB */ XEN_CPUFEATURE(INVPCID, 5*32+10) /* Invalidate Process Context ID */ XEN_CPUFEATURE(RTM, 5*32+11) /* Restricted Transactional Memory */ XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ -XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /* FPU CS/DS stored as zero */ +XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ XEN_CPUFEATURE(MPX, 5*32+14) /* Memory Protection Extensions */ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ XEN_CPUFEATURE(RDSEED, 5*32+18) /* RDSEED instruction */ @@ -208,7 +220,7 @@ XEN_CPUFEATURE(SHA, 5*32+29) /* SHA1 & SHA256 instructions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /* PREFETCHWT1 instruction */ XEN_CPUFEATURE(PKU, 6*32+ 3) /* Protection Keys for Userspace */ -XEN_CPUFEATURE(OSPKE, 6*32+ 4) /* OS Protection Keys Enable */ +XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index ca413f8..5171c6e 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -16,11 +16,13 @@ class State(object): # State parsed from input self.names = {} # Name => value mapping + self.raw_special = set() # State calculated self.nr_entries = 0 # Number of words in a featureset self.common_1d = 0 # Common features between 1d and e1d self.known = [] # All known features + self.special = [] # Features with special semantics def parse_definitions(state): """ @@ -29,7 +31,8 @@ def parse_definitions(state): """ feat_regex = re.compile( r"^XEN_CPUFEATURE\(([A-Z0-9_]+)," - "\s+([\s\d]+\*[\s\d]+\+[\s\d]+)\).*$") + "\s+([\s\d]+\*[\s\d]+\+[\s\d]+)\)" + "\s+/\*([!]*) .*$") this = sys.modules[__name__] @@ -45,6 +48,7 @@ def parse_definitions(state): name = res.groups()[0] val = eval(res.groups()[1]) # Regex confines this to a very simple expression + attr = res.groups()[2] if hasattr(this, name): raise Fail("Duplicate symbol %s" % (name,)) @@ -64,6 +68,13 @@ def parse_definitions(state): # Construct a reverse mapping of value to name state.names[val] = name + for a in attr: + + if a == "!": + state.raw_special.add(val) + else: + raise Fail("Unrecognised attribute '%s' for %s" % (a, name)) + if len(state.names) == 0: raise Fail("No features found") @@ -112,6 +123,7 @@ def crunch_numbers(state): state.names[e1d_base + (f % 32)] = "E1D_" + state.names[f] state.common_1d = featureset_to_uint32s(common_1d, 1)[0] + state.special = featureset_to_uint32s(state.raw_special, nr_entries) def write_results(state): @@ -131,9 +143,12 @@ def write_results(state): #define CPUID_COMMON_1D_FEATURES %s #define INIT_KNOWN_FEATURES { \\\n%s\n} + +#define INIT_SPECIAL_FEATURES { \\\n%s\n} """ % (state.nr_entries, state.common_1d, format_uint32s(state.known, 4), + format_uint32s(state.special, 4), )) state.output.write(