| Message ID | 1458056124-8024-9-git-send-email-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Mar 15, 2016 at 03:35:04PM +0000, Andrew Cooper wrote: > Use attributes to specify whether a feature is applicable to be exposed to: > 1) All guests > 2) HVM guests > 3) HVM HAP guests > > There is no current need for other categories (e.g. PV-only features), and > such categories shoud not be introduced if possible. These categories follow /shoud/should/ > from the fact that, with increased hardware support, a guest gets more > features to use. > > These settings are derived from the existing code in {pv,hvm}_cpuid(), and Yikes. That must have taken a while to dig. > xc_cpuid_x86.c. One notable excetpion is EXTAPIC which was previously > erroniously exposed to guests. PV guests don't get to use the APIC and the > HVM APIC emulation doesn't support extended space. I would extend this commit description (right after 3)) and the comment below to say: If they are not set - the guest will not see this flag. Otherwise: Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> > --- > CC: Jan Beulich <JBeulich@suse.com> > > v3: > * Rebase over the new namespaceing changes. > * Expand commit message. > * Correct PSE36 to being a HAP-only feature. > > v2: > * Annotate features using a magic comment and autogeneration. > --- > xen/include/public/arch-x86/cpufeatureset.h | 187 ++++++++++++++-------------- > xen/tools/gen-cpuid.py | 30 ++++- > 2 files changed, 125 insertions(+), 92 deletions(-) > > diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h > index 9389ed9..2a13e0c 100644 > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -91,135 +91,140 @@ enum { > * This bit has special properties and is not a straight indication of a > * piece of new functionality. Xen will handle these differently, > * and may override toolstack settings completely. > + * > + * Applicability to guests: 'A', 'S' or 'H' > + * 'A' = All guests. > + * 'S' = All HVM guests (not PV guests). > + * 'H' = HVM HAP guests (not PV or HVM Shadow guests). > */ > > /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ > -XEN_CPUFEATURE(FPU, 0*32+ 0) /* Onboard FPU */ > -XEN_CPUFEATURE(VME, 0*32+ 1) /* Virtual Mode Extensions */ > -XEN_CPUFEATURE(DE, 0*32+ 2) /* Debugging Extensions */ > -XEN_CPUFEATURE(PSE, 0*32+ 3) /* Page Size Extensions */ > -XEN_CPUFEATURE(TSC, 0*32+ 4) /* Time Stamp Counter */ > -XEN_CPUFEATURE(MSR, 0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ > -XEN_CPUFEATURE(PAE, 0*32+ 6) /* Physical Address Extensions */ > -XEN_CPUFEATURE(MCE, 0*32+ 7) /* Machine Check Architecture */ > -XEN_CPUFEATURE(CX8, 0*32+ 8) /* CMPXCHG8 instruction */ > -XEN_CPUFEATURE(APIC, 0*32+ 9) /*! Onboard APIC */ > -XEN_CPUFEATURE(SEP, 0*32+11) /* SYSENTER/SYSEXIT */ > -XEN_CPUFEATURE(MTRR, 0*32+12) /* Memory Type Range Registers */ > -XEN_CPUFEATURE(PGE, 0*32+13) /* Page Global Enable */ > -XEN_CPUFEATURE(MCA, 0*32+14) /* Machine Check Architecture */ > -XEN_CPUFEATURE(CMOV, 0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ > -XEN_CPUFEATURE(PAT, 0*32+16) /* Page Attribute Table */ > -XEN_CPUFEATURE(PSE36, 0*32+17) /* 36-bit PSEs */ > -XEN_CPUFEATURE(CLFLUSH, 0*32+19) /* CLFLUSH instruction */ > +XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ > +XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ > +XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ > +XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ > +XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ > +XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ > +XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ > +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ > +XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ > +XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ > +XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ > +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ > +XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ > +XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ > +XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ > +XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ > +XEN_CPUFEATURE(PSE36, 0*32+17) /*H 36-bit PSEs */ > +XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ > XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ > -XEN_CPUFEATURE(ACPI, 0*32+22) /* ACPI via MSR */ > -XEN_CPUFEATURE(MMX, 0*32+23) /* Multimedia Extensions */ > -XEN_CPUFEATURE(FXSR, 0*32+24) /* FXSAVE and FXRSTOR instructions */ > -XEN_CPUFEATURE(SSE, 0*32+25) /* Streaming SIMD Extensions */ > -XEN_CPUFEATURE(SSE2, 0*32+26) /* Streaming SIMD Extensions-2 */ > -XEN_CPUFEATURE(HTT, 0*32+28) /*! Hyper-Threading Technology */ > +XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ > +XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ > +XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ > +XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ > +XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ > +XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ > XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ > XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ > > /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ > -XEN_CPUFEATURE(SSE3, 1*32+ 0) /* Streaming SIMD Extensions-3 */ > -XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /* Carry-less mulitplication */ > +XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ > +XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less mulitplication */ > XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ > XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ > XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ > -XEN_CPUFEATURE(VMX, 1*32+ 5) /* Virtual Machine Extensions */ > +XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */ > XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ > XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ > XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ > -XEN_CPUFEATURE(SSSE3, 1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */ > -XEN_CPUFEATURE(FMA, 1*32+12) /* Fused Multiply Add */ > -XEN_CPUFEATURE(CX16, 1*32+13) /* CMPXCHG16B */ > +XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ > +XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ > +XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ > XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ > XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ > -XEN_CPUFEATURE(PCID, 1*32+17) /* Process Context ID */ > +XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ > XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ > -XEN_CPUFEATURE(SSE4_1, 1*32+19) /* Streaming SIMD Extensions 4.1 */ > -XEN_CPUFEATURE(SSE4_2, 1*32+20) /* Streaming SIMD Extensions 4.2 */ > -XEN_CPUFEATURE(X2APIC, 1*32+21) /* Extended xAPIC */ > -XEN_CPUFEATURE(MOVBE, 1*32+22) /* movbe instruction */ > -XEN_CPUFEATURE(POPCNT, 1*32+23) /* POPCNT instruction */ > -XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /* TSC Deadline Timer */ > -XEN_CPUFEATURE(AESNI, 1*32+25) /* AES instructions */ > -XEN_CPUFEATURE(XSAVE, 1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ > +XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ > +XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ > +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ > +XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ > +XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ > +XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ > +XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ > +XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ > XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ > -XEN_CPUFEATURE(AVX, 1*32+28) /* Advanced Vector Extensions */ > -XEN_CPUFEATURE(F16C, 1*32+29) /* Half-precision convert instruction */ > -XEN_CPUFEATURE(RDRAND, 1*32+30) /* Digital Random Number Generator */ > -XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /* Running under some hypervisor */ > +XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ > +XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ > +XEN_CPUFEATURE(RDRAND, 1*32+30) /*A Digital Random Number Generator */ > +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ > > /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ > -XEN_CPUFEATURE(SYSCALL, 2*32+11) /* SYSCALL/SYSRET */ > -XEN_CPUFEATURE(NX, 2*32+20) /* Execute Disable */ > -XEN_CPUFEATURE(MMXEXT, 2*32+22) /* AMD MMX extensions */ > -XEN_CPUFEATURE(FFXSR, 2*32+25) /* FFXSR instruction optimizations */ > -XEN_CPUFEATURE(PAGE1GB, 2*32+26) /* 1Gb large page support */ > -XEN_CPUFEATURE(RDTSCP, 2*32+27) /* RDTSCP */ > -XEN_CPUFEATURE(LM, 2*32+29) /* Long Mode (x86-64) */ > -XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /* AMD 3DNow! extensions */ > -XEN_CPUFEATURE(3DNOW, 2*32+31) /* 3DNow! */ > +XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ > +XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ > +XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ > +XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ > +XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ > +XEN_CPUFEATURE(RDTSCP, 2*32+27) /*S RDTSCP */ > +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ > +XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ > +XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ > > /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ > -XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /* LAHF/SAHF in long mode */ > -XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*! If yes HyperThreading not valid */ > -XEN_CPUFEATURE(SVM, 3*32+ 2) /* Secure virtual machine */ > +XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ > +XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ > +XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */ > XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ > -XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /* CR8 in 32-bit mode */ > -XEN_CPUFEATURE(ABM, 3*32+ 5) /* Advanced bit manipulation */ > -XEN_CPUFEATURE(SSE4A, 3*32+ 6) /* SSE-4A */ > -XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /* Misaligned SSE mode */ > -XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /* 3DNow prefetch instructions */ > +XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ > +XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ > +XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ > +XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ > +XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ > XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ > -XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ > -XEN_CPUFEATURE(XOP, 3*32+11) /* extended AVX instructions */ > +XEN_CPUFEATURE(IBS, 3*32+10) /*S Instruction Based Sampling */ > +XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ > XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ > XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ > -XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ > -XEN_CPUFEATURE(FMA4, 3*32+16) /* 4 operands MAC instructions */ > +XEN_CPUFEATURE(LWP, 3*32+15) /*A Light Weight Profiling */ > +XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ > XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ > -XEN_CPUFEATURE(TBM, 3*32+21) /* trailing bit manipulations */ > +XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ > XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ > -XEN_CPUFEATURE(DBEXT, 3*32+26) /* data breakpoint extension */ > +XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ > XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ > > /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ > -XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /* XSAVEOPT instruction */ > -XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /* XSAVEC/XRSTORC instructions */ > -XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /* XGETBV with %ecx=1 */ > -XEN_CPUFEATURE(XSAVES, 4*32+ 3) /* XSAVES/XRSTORS instructions */ > +XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ > +XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ > +XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ > +XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ > > /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ > -XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ > -XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /* TSC_ADJUST MSR available */ > -XEN_CPUFEATURE(BMI1, 5*32+ 3) /* 1st bit manipulation extensions */ > -XEN_CPUFEATURE(HLE, 5*32+ 4) /* Hardware Lock Elision */ > -XEN_CPUFEATURE(AVX2, 5*32+ 5) /* AVX2 instructions */ > +XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ > +XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ > +XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ > +XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ > +XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ > XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ > -XEN_CPUFEATURE(SMEP, 5*32+ 7) /* Supervisor Mode Execution Protection */ > -XEN_CPUFEATURE(BMI2, 5*32+ 8) /* 2nd bit manipulation extensions */ > -XEN_CPUFEATURE(ERMS, 5*32+ 9) /* Enhanced REP MOVSB/STOSB */ > -XEN_CPUFEATURE(INVPCID, 5*32+10) /* Invalidate Process Context ID */ > -XEN_CPUFEATURE(RTM, 5*32+11) /* Restricted Transactional Memory */ > +XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ > +XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ > +XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ > +XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ > +XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */ > XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ > XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ > -XEN_CPUFEATURE(MPX, 5*32+14) /* Memory Protection Extensions */ > +XEN_CPUFEATURE(MPX, 5*32+14) /*S Memory Protection Extensions */ > XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ > -XEN_CPUFEATURE(RDSEED, 5*32+18) /* RDSEED instruction */ > -XEN_CPUFEATURE(ADX, 5*32+19) /* ADCX, ADOX instructions */ > -XEN_CPUFEATURE(SMAP, 5*32+20) /* Supervisor Mode Access Prevention */ > -XEN_CPUFEATURE(PCOMMIT, 5*32+22) /* PCOMMIT instruction */ > -XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /* CLFLUSHOPT instruction */ > -XEN_CPUFEATURE(CLWB, 5*32+24) /* CLWB instruction */ > -XEN_CPUFEATURE(SHA, 5*32+29) /* SHA1 & SHA256 instructions */ > +XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ > +XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ > +XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ > +XEN_CPUFEATURE(PCOMMIT, 5*32+22) /*A PCOMMIT instruction */ > +XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ > +XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ > +XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ > > /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ > -XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /* PREFETCHWT1 instruction */ > -XEN_CPUFEATURE(PKU, 6*32+ 3) /* Protection Keys for Userspace */ > +XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ > +XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ > XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ > > /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ > @@ -227,7 +232,7 @@ XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ > XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ > > /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ > -XEN_CPUFEATURE(CLZERO, 8*32+ 0) /* CLZERO instruction */ > +XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ > > #endif /* XEN_CPUFEATURE */ > > diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py > index 5171c6e..452c26a 100755 > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -17,12 +17,18 @@ class State(object): > # State parsed from input > self.names = {} # Name => value mapping > self.raw_special = set() > + self.raw_pv = set() > + self.raw_hvm_shadow = set() > + self.raw_hvm_hap = set() > > # State calculated > self.nr_entries = 0 # Number of words in a featureset > self.common_1d = 0 # Common features between 1d and e1d > self.known = [] # All known features > self.special = [] # Features with special semantics > + self.pv = [] > + self.hvm_shadow = [] > + self.hvm_hap = [] > > def parse_definitions(state): > """ > @@ -32,7 +38,7 @@ def parse_definitions(state): > feat_regex = re.compile( > r"^XEN_CPUFEATURE\(([A-Z0-9_]+)," > "\s+([\s\d]+\*[\s\d]+\+[\s\d]+)\)" > - "\s+/\*([!]*) .*$") > + "\s+/\*([\w!]*) .*$") > > this = sys.modules[__name__] > > @@ -72,6 +78,16 @@ def parse_definitions(state): > > if a == "!": > state.raw_special.add(val) > + elif a in "ASH": > + if a == "A": > + state.raw_pv.add(val) > + state.raw_hvm_shadow.add(val) > + state.raw_hvm_hap.add(val) > + elif attr == "S": > + state.raw_hvm_shadow.add(val) > + state.raw_hvm_hap.add(val) > + elif attr == "H": > + state.raw_hvm_hap.add(val) > else: > raise Fail("Unrecognised attribute '%s' for %s" % (a, name)) > > @@ -124,6 +140,9 @@ def crunch_numbers(state): > > state.common_1d = featureset_to_uint32s(common_1d, 1)[0] > state.special = featureset_to_uint32s(state.raw_special, nr_entries) > + state.pv = featureset_to_uint32s(state.raw_pv, nr_entries) > + state.hvm_shadow = featureset_to_uint32s(state.raw_hvm_shadow, nr_entries) > + state.hvm_hap = featureset_to_uint32s(state.raw_hvm_hap, nr_entries) > > > def write_results(state): > @@ -145,10 +164,19 @@ def write_results(state): > #define INIT_KNOWN_FEATURES { \\\n%s\n} > > #define INIT_SPECIAL_FEATURES { \\\n%s\n} > + > +#define INIT_PV_FEATURES { \\\n%s\n} > + > +#define INIT_HVM_SHADOW_FEATURES { \\\n%s\n} > + > +#define INIT_HVM_HAP_FEATURES { \\\n%s\n} > """ % (state.nr_entries, > state.common_1d, > format_uint32s(state.known, 4), > format_uint32s(state.special, 4), > + format_uint32s(state.pv, 4), > + format_uint32s(state.hvm_shadow, 4), > + format_uint32s(state.hvm_hap, 4), > )) > > state.output.write( > -- > 2.1.4 > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel
>>> On 15.03.16 at 16:35, <andrew.cooper3@citrix.com> wrote: > v3: > * Rebase over the new namespaceing changes. > * Expand commit message. > * Correct PSE36 to being a HAP-only feature. As Tim has pointed out on IRC, this may need revisiting. > +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ Exposing MCA makes sense, but do we really need to expose MCE too? > +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ I thin I've said so before - this alters current behavior, and is pretty certainly wrong for PV Dom0. > XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ Is leaving this unexposed compatible with vPMU (would then presumably also apply to DTES64 and DSCPL)? > +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ Does this make sense for PV? > +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ Wouldn't this better be one of the special ones? > +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ I think I had asked before, but doesn't the customization needed for 32-bit PV guests also rather make this a special one? Or if not, perhaps the commit message could be made say a word on the intention regarding runtime overrides to these statically determine sets? > +XEN_CPUFEATURE(LWP, 3*32+15) /*A Light Weight Profiling */ Right now this gets cleared by pv_cpuid(), so I think this needs to be S. Jan
On 18/03/16 16:57, Jan Beulich wrote: >>>> On 15.03.16 at 16:35, <andrew.cooper3@citrix.com> wrote: >> v3: >> * Rebase over the new namespaceing changes. >> * Expand commit message. >> * Correct PSE36 to being a HAP-only feature. > As Tim has pointed out on IRC, this may need revisiting. I am still debating how to fix this. I absolutely don't want to pollute Xen with an architecturally-wrong workaround for a bug some unidentified version of HyperV from 2011. > >> +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ > Exposing MCA makes sense, but do we really need to expose MCE > too? CR4.MCE leaks into PV guests. > >> +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ > I thin I've said so before - this alters current behavior Again, no it doesn't. PV DomU's don't get to see MTRR; the feature is clobbered in the toolstack. > , and is pretty certainly wrong for PV Dom0. And again, no it very much isn't. PV guests cannot use MTRRs, so shouldn't see the feature. PVOPS specifically self-knobbles MTRR if it is found in the cpuid leaves (enlighten.c: xen_init_cpuid_mask()). classic-xen kernels don't even look at the feature bit if they are not dom0. I presume your complaint is because SUSE are still using a classic-xen dom0 kernel? The check is already buggy because there is no guarantee (or reasonable expectation) that Xen has MTRRs to use in the first place. Why don't you fix this by checking for what the mtrr driver is actually using, i.e. the presence of the XENPF_add_memtype hypercall, which could be implemented in Xen using PAT? I could be persuaded to implement a dom0 specific override in pv_cpuid() to cover the buggy cases, but this line of code is not changing. > >> XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ > Is leaving this unexposed compatible with vPMU (would then > presumably also apply to DTES64 and DSCPL)? vPMU modification happens after masking, so this doesn't interfere with anything. > >> +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ > Does this make sense for PV? It is currently visible, and we already have to leak APIC through to PV guests. > >> +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ > Wouldn't this better be one of the special ones? Why? It doesn't need any special handling in Xen. For all intents and purposes, it is just like a regular feature bit. > >> +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ > I think I had asked before, but doesn't the customization needed > for 32-bit PV guests also rather make this a special one? Why would it? It is a simple feature which isn't present for 32bit guests. > Or if not, perhaps the commit message could be made say a word on the > intention regarding runtime overrides to these statically determine > sets? In this series, libxc can calculate this and sets it appropriately for each domain. Xen currently lacks a per-domain policy, so doesn't audit the validity of the data in the set_cpuid_policy hypercall. As a buggy toolstack could send bad policy data, the runtime checks are kept for safety. Once this series is accepted, I will be working on the next phase, which will include per-domain policies, and auditing for correctness at the hypercall boundary. Once this infrastructure is complete, the runtime overrides will be removed. > >> +XEN_CPUFEATURE(LWP, 3*32+15) /*A Light Weight Profiling */ > Right now this gets cleared by pv_cpuid(), so I think this needs to > be S.# So it does. Yes it should. ~Andrew
>>> On 18.03.16 at 19:56, <andrew.cooper3@citrix.com> wrote: > On 18/03/16 16:57, Jan Beulich wrote: >>>>> On 15.03.16 at 16:35, <andrew.cooper3@citrix.com> wrote: >>> +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ >> I thin I've said so before - this alters current behavior > > Again, no it doesn't. PV DomU's don't get to see MTRR; the feature is > clobbered in the toolstack. Ah, indeed. >> , and is pretty certainly wrong for PV Dom0. > > And again, no it very much isn't. PV guests cannot use MTRRs, so > shouldn't see the feature. > > PVOPS specifically self-knobbles MTRR if it is found in the cpuid leaves > (enlighten.c: xen_init_cpuid_mask()). classic-xen kernels don't even > look at the feature bit if they are not dom0. > > I presume your complaint is because SUSE are still using a classic-xen > dom0 kernel? The check is already buggy because there is no guarantee > (or reasonable expectation) that Xen has MTRRs to use in the first > place. Why don't you fix this by checking for what the mtrr driver is > actually using, i.e. the presence of the XENPF_add_memtype hypercall, > which could be implemented in Xen using PAT? Well, it has always been my understanding that the CPUID MTRR bit to a PV guest means just that - availability of the respective hypercalls. Also note that whatever change I might do to the old sources, it wouldn't help with existing kernel binaries, which you must not break. > I could be persuaded to implement a dom0 specific override in pv_cpuid() > to cover the buggy cases, but this line of code is not changing. And I'm fine with such an override, but please make not of such special cases in the commit message, so the question won't come up again and again (by me or future readers). >>> +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ >> Does this make sense for PV? > > It is currently visible, and we already have to leak APIC through to PV > guests. Having to leak on piece of state doesn't mean when need to leak more, when that's clearly impossibly to be meaningful to a guest. >>> +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ >> Wouldn't this better be one of the special ones? > > Why? It doesn't need any special handling in Xen. For all intents and > purposes, it is just like a regular feature bit. Except that you don't pass through its host value, but instead override it to 1. Which makes it kind of special, I would say. >>> +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ >> I think I had asked before, but doesn't the customization needed >> for 32-bit PV guests also rather make this a special one? > > Why would it? It is a simple feature which isn't present for 32bit guests. Together with the above the question really is: What exactly makes a feature special? The need for run time overrides, or something more sophisticated? Jan
On 21/03/16 11:53, Jan Beulich wrote: >>>> +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ >>> Does this make sense for PV? >> It is currently visible, and we already have to leak APIC through to PV >> guests. > Having to leak on piece of state doesn't mean when need to leak > more, when that's clearly impossibly to be meaningful to a guest. PV guests can already real real APIC IDs out cpu leaves in the masking case. Now I think about it, this is special just like HTT and CMP_LEGACY, and must have the host value leaked through to PV guests when masking is in effect. >>>> +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ >>> Wouldn't this better be one of the special ones? >> Why? It doesn't need any special handling in Xen. For all intents and >> purposes, it is just like a regular feature bit. > Except that you don't pass through its host value, but instead > override it to 1. Which makes it kind of special, I would say. HVM guests go straight from the toolstack settings. PV guests have it unilaterally set. I suppose this does qualify for special under the guidelines I was using. I suspect it is only unilaterally set so it appears as set to dom0. DomUs also have it unilaterally set by the toolstack. I suspect it makes very little difference for a PV guest, which knows for certain that it is virtualised. >>>> +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ >>> I think I had asked before, but doesn't the customization needed >>> for 32-bit PV guests also rather make this a special one? >> Why would it? It is a simple feature which isn't present for 32bit guests. > Together with the above the question really is: What exactly makes > a feature special? The need for run time overrides, or something > more sophisticated? "Things which Xen has to deal specially with", which includes conditionally leaking host state through. ~Andrew
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 9389ed9..2a13e0c 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -91,135 +91,140 @@ enum { * This bit has special properties and is not a straight indication of a * piece of new functionality. Xen will handle these differently, * and may override toolstack settings completely. + * + * Applicability to guests: 'A', 'S' or 'H' + * 'A' = All guests. + * 'S' = All HVM guests (not PV guests). + * 'H' = HVM HAP guests (not PV or HVM Shadow guests). */ /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ -XEN_CPUFEATURE(FPU, 0*32+ 0) /* Onboard FPU */ -XEN_CPUFEATURE(VME, 0*32+ 1) /* Virtual Mode Extensions */ -XEN_CPUFEATURE(DE, 0*32+ 2) /* Debugging Extensions */ -XEN_CPUFEATURE(PSE, 0*32+ 3) /* Page Size Extensions */ -XEN_CPUFEATURE(TSC, 0*32+ 4) /* Time Stamp Counter */ -XEN_CPUFEATURE(MSR, 0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ -XEN_CPUFEATURE(PAE, 0*32+ 6) /* Physical Address Extensions */ -XEN_CPUFEATURE(MCE, 0*32+ 7) /* Machine Check Architecture */ -XEN_CPUFEATURE(CX8, 0*32+ 8) /* CMPXCHG8 instruction */ -XEN_CPUFEATURE(APIC, 0*32+ 9) /*! Onboard APIC */ -XEN_CPUFEATURE(SEP, 0*32+11) /* SYSENTER/SYSEXIT */ -XEN_CPUFEATURE(MTRR, 0*32+12) /* Memory Type Range Registers */ -XEN_CPUFEATURE(PGE, 0*32+13) /* Page Global Enable */ -XEN_CPUFEATURE(MCA, 0*32+14) /* Machine Check Architecture */ -XEN_CPUFEATURE(CMOV, 0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ -XEN_CPUFEATURE(PAT, 0*32+16) /* Page Attribute Table */ -XEN_CPUFEATURE(PSE36, 0*32+17) /* 36-bit PSEs */ -XEN_CPUFEATURE(CLFLUSH, 0*32+19) /* CLFLUSH instruction */ +XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ +XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ +XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ +XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ +XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ +XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ +XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ +XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ +XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ +XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ +XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ +XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ +XEN_CPUFEATURE(PSE36, 0*32+17) /*H 36-bit PSEs */ +XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ -XEN_CPUFEATURE(ACPI, 0*32+22) /* ACPI via MSR */ -XEN_CPUFEATURE(MMX, 0*32+23) /* Multimedia Extensions */ -XEN_CPUFEATURE(FXSR, 0*32+24) /* FXSAVE and FXRSTOR instructions */ -XEN_CPUFEATURE(SSE, 0*32+25) /* Streaming SIMD Extensions */ -XEN_CPUFEATURE(SSE2, 0*32+26) /* Streaming SIMD Extensions-2 */ -XEN_CPUFEATURE(HTT, 0*32+28) /*! Hyper-Threading Technology */ +XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ +XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ +XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ +XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ +XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ +XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ -XEN_CPUFEATURE(SSE3, 1*32+ 0) /* Streaming SIMD Extensions-3 */ -XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /* Carry-less mulitplication */ +XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less mulitplication */ XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ -XEN_CPUFEATURE(VMX, 1*32+ 5) /* Virtual Machine Extensions */ +XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */ XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ -XEN_CPUFEATURE(SSSE3, 1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */ -XEN_CPUFEATURE(FMA, 1*32+12) /* Fused Multiply Add */ -XEN_CPUFEATURE(CX16, 1*32+13) /* CMPXCHG16B */ +XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ +XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ -XEN_CPUFEATURE(PCID, 1*32+17) /* Process Context ID */ +XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ -XEN_CPUFEATURE(SSE4_1, 1*32+19) /* Streaming SIMD Extensions 4.1 */ -XEN_CPUFEATURE(SSE4_2, 1*32+20) /* Streaming SIMD Extensions 4.2 */ -XEN_CPUFEATURE(X2APIC, 1*32+21) /* Extended xAPIC */ -XEN_CPUFEATURE(MOVBE, 1*32+22) /* movbe instruction */ -XEN_CPUFEATURE(POPCNT, 1*32+23) /* POPCNT instruction */ -XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /* TSC Deadline Timer */ -XEN_CPUFEATURE(AESNI, 1*32+25) /* AES instructions */ -XEN_CPUFEATURE(XSAVE, 1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ +XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ +XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ +XEN_CPUFEATURE(X2APIC, 1*32+21) /*A Extended xAPIC */ +XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ +XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ +XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ +XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ +XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ -XEN_CPUFEATURE(AVX, 1*32+28) /* Advanced Vector Extensions */ -XEN_CPUFEATURE(F16C, 1*32+29) /* Half-precision convert instruction */ -XEN_CPUFEATURE(RDRAND, 1*32+30) /* Digital Random Number Generator */ -XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /* Running under some hypervisor */ +XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ +XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ +XEN_CPUFEATURE(RDRAND, 1*32+30) /*A Digital Random Number Generator */ +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*A Running under some hypervisor */ /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ -XEN_CPUFEATURE(SYSCALL, 2*32+11) /* SYSCALL/SYSRET */ -XEN_CPUFEATURE(NX, 2*32+20) /* Execute Disable */ -XEN_CPUFEATURE(MMXEXT, 2*32+22) /* AMD MMX extensions */ -XEN_CPUFEATURE(FFXSR, 2*32+25) /* FFXSR instruction optimizations */ -XEN_CPUFEATURE(PAGE1GB, 2*32+26) /* 1Gb large page support */ -XEN_CPUFEATURE(RDTSCP, 2*32+27) /* RDTSCP */ -XEN_CPUFEATURE(LM, 2*32+29) /* Long Mode (x86-64) */ -XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /* AMD 3DNow! extensions */ -XEN_CPUFEATURE(3DNOW, 2*32+31) /* 3DNow! */ +XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ +XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ +XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ +XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ +XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ +XEN_CPUFEATURE(RDTSCP, 2*32+27) /*S RDTSCP */ +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ +XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ +XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ -XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /* LAHF/SAHF in long mode */ -XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*! If yes HyperThreading not valid */ -XEN_CPUFEATURE(SVM, 3*32+ 2) /* Secure virtual machine */ +XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ +XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ +XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */ XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ -XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /* CR8 in 32-bit mode */ -XEN_CPUFEATURE(ABM, 3*32+ 5) /* Advanced bit manipulation */ -XEN_CPUFEATURE(SSE4A, 3*32+ 6) /* SSE-4A */ -XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /* Misaligned SSE mode */ -XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /* 3DNow prefetch instructions */ +XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ +XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ +XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ +XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ +XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ -XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ -XEN_CPUFEATURE(XOP, 3*32+11) /* extended AVX instructions */ +XEN_CPUFEATURE(IBS, 3*32+10) /*S Instruction Based Sampling */ +XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ -XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ -XEN_CPUFEATURE(FMA4, 3*32+16) /* 4 operands MAC instructions */ +XEN_CPUFEATURE(LWP, 3*32+15) /*A Light Weight Profiling */ +XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ -XEN_CPUFEATURE(TBM, 3*32+21) /* trailing bit manipulations */ +XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ -XEN_CPUFEATURE(DBEXT, 3*32+26) /* data breakpoint extension */ +XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ -XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /* XSAVEOPT instruction */ -XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /* XSAVEC/XRSTORC instructions */ -XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /* XGETBV with %ecx=1 */ -XEN_CPUFEATURE(XSAVES, 4*32+ 3) /* XSAVES/XRSTORS instructions */ +XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ +XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ +XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ +XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ -XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ -XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /* TSC_ADJUST MSR available */ -XEN_CPUFEATURE(BMI1, 5*32+ 3) /* 1st bit manipulation extensions */ -XEN_CPUFEATURE(HLE, 5*32+ 4) /* Hardware Lock Elision */ -XEN_CPUFEATURE(AVX2, 5*32+ 5) /* AVX2 instructions */ +XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ +XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ +XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ +XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ +XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ -XEN_CPUFEATURE(SMEP, 5*32+ 7) /* Supervisor Mode Execution Protection */ -XEN_CPUFEATURE(BMI2, 5*32+ 8) /* 2nd bit manipulation extensions */ -XEN_CPUFEATURE(ERMS, 5*32+ 9) /* Enhanced REP MOVSB/STOSB */ -XEN_CPUFEATURE(INVPCID, 5*32+10) /* Invalidate Process Context ID */ -XEN_CPUFEATURE(RTM, 5*32+11) /* Restricted Transactional Memory */ +XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ +XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ +XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ +XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ +XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */ XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ -XEN_CPUFEATURE(MPX, 5*32+14) /* Memory Protection Extensions */ +XEN_CPUFEATURE(MPX, 5*32+14) /*S Memory Protection Extensions */ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ -XEN_CPUFEATURE(RDSEED, 5*32+18) /* RDSEED instruction */ -XEN_CPUFEATURE(ADX, 5*32+19) /* ADCX, ADOX instructions */ -XEN_CPUFEATURE(SMAP, 5*32+20) /* Supervisor Mode Access Prevention */ -XEN_CPUFEATURE(PCOMMIT, 5*32+22) /* PCOMMIT instruction */ -XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /* CLFLUSHOPT instruction */ -XEN_CPUFEATURE(CLWB, 5*32+24) /* CLWB instruction */ -XEN_CPUFEATURE(SHA, 5*32+29) /* SHA1 & SHA256 instructions */ +XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ +XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ +XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ +XEN_CPUFEATURE(PCOMMIT, 5*32+22) /*A PCOMMIT instruction */ +XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ +XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ -XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /* PREFETCHWT1 instruction */ -XEN_CPUFEATURE(PKU, 6*32+ 3) /* Protection Keys for Userspace */ +XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ +XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ @@ -227,7 +232,7 @@ XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ -XEN_CPUFEATURE(CLZERO, 8*32+ 0) /* CLZERO instruction */ +XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ #endif /* XEN_CPUFEATURE */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 5171c6e..452c26a 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -17,12 +17,18 @@ class State(object): # State parsed from input self.names = {} # Name => value mapping self.raw_special = set() + self.raw_pv = set() + self.raw_hvm_shadow = set() + self.raw_hvm_hap = set() # State calculated self.nr_entries = 0 # Number of words in a featureset self.common_1d = 0 # Common features between 1d and e1d self.known = [] # All known features self.special = [] # Features with special semantics + self.pv = [] + self.hvm_shadow = [] + self.hvm_hap = [] def parse_definitions(state): """ @@ -32,7 +38,7 @@ def parse_definitions(state): feat_regex = re.compile( r"^XEN_CPUFEATURE\(([A-Z0-9_]+)," "\s+([\s\d]+\*[\s\d]+\+[\s\d]+)\)" - "\s+/\*([!]*) .*$") + "\s+/\*([\w!]*) .*$") this = sys.modules[__name__] @@ -72,6 +78,16 @@ def parse_definitions(state): if a == "!": state.raw_special.add(val) + elif a in "ASH": + if a == "A": + state.raw_pv.add(val) + state.raw_hvm_shadow.add(val) + state.raw_hvm_hap.add(val) + elif attr == "S": + state.raw_hvm_shadow.add(val) + state.raw_hvm_hap.add(val) + elif attr == "H": + state.raw_hvm_hap.add(val) else: raise Fail("Unrecognised attribute '%s' for %s" % (a, name)) @@ -124,6 +140,9 @@ def crunch_numbers(state): state.common_1d = featureset_to_uint32s(common_1d, 1)[0] state.special = featureset_to_uint32s(state.raw_special, nr_entries) + state.pv = featureset_to_uint32s(state.raw_pv, nr_entries) + state.hvm_shadow = featureset_to_uint32s(state.raw_hvm_shadow, nr_entries) + state.hvm_hap = featureset_to_uint32s(state.raw_hvm_hap, nr_entries) def write_results(state): @@ -145,10 +164,19 @@ def write_results(state): #define INIT_KNOWN_FEATURES { \\\n%s\n} #define INIT_SPECIAL_FEATURES { \\\n%s\n} + +#define INIT_PV_FEATURES { \\\n%s\n} + +#define INIT_HVM_SHADOW_FEATURES { \\\n%s\n} + +#define INIT_HVM_HAP_FEATURES { \\\n%s\n} """ % (state.nr_entries, state.common_1d, format_uint32s(state.known, 4), format_uint32s(state.special, 4), + format_uint32s(state.pv, 4), + format_uint32s(state.hvm_shadow, 4), + format_uint32s(state.hvm_hap, 4), )) state.output.write(
Use attributes to specify whether a feature is applicable to be exposed to: 1) All guests 2) HVM guests 3) HVM HAP guests There is no current need for other categories (e.g. PV-only features), and such categories shoud not be introduced if possible. These categories follow from the fact that, with increased hardware support, a guest gets more features to use. These settings are derived from the existing code in {pv,hvm}_cpuid(), and xc_cpuid_x86.c. One notable excetpion is EXTAPIC which was previously erroniously exposed to guests. PV guests don't get to use the APIC and the HVM APIC emulation doesn't support extended space. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> v3: * Rebase over the new namespaceing changes. * Expand commit message. * Correct PSE36 to being a HAP-only feature. v2: * Annotate features using a magic comment and autogeneration. --- xen/include/public/arch-x86/cpufeatureset.h | 187 ++++++++++++++-------------- xen/tools/gen-cpuid.py | 30 ++++- 2 files changed, 125 insertions(+), 92 deletions(-)