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banners=-,-,- X-VirusChecked: Checked Received: (qmail 34181 invoked from network); 23 May 2016 14:17:49 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-206.messagelabs.com with SMTP; 23 May 2016 14:17:49 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63EA03C; Mon, 23 May 2016 07:18:11 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DFE13F21A; Mon, 23 May 2016 07:17:47 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 23 May 2016 15:17:22 +0100 Message-Id: <1464013052-32587-6-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464013052-32587-1-git-send-email-julien.grall@arm.com> References: <1464013052-32587-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.liu2@citrix.com, steve.capper@arm.com, andre.przywara@arm.com, Julien Grall , wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 05/15] xen/arm64: Add an helper to invalidate all instruction caches X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add Stefano's acked-by --- xen/include/asm-arm/arm64/page.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 29a32cf..fbdc8fb 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -24,6 +24,12 @@ static inline void write_pte(lpae_t *p, lpae_t pte) * inline asm operand) */ #define __clean_and_invalidate_dcache_one(R) "dc civac, %" #R ";" +/* Invalidate all instruction caches in Inner Shareable domain to PoU */ +static inline void invalidate_icache(void) +{ + asm volatile ("ic ialluis"); +} + /* * Flush all hypervisor mappings from the TLB of the local processor. *