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Tue, 24 May 2016 19:09:59 -0700 (PDT) Received: from localhost.members.linode.com ([2400:8900::f03c:91ff:fe56:1324]) by smtp.gmail.com with ESMTPSA id y3sm8195655par.2.2016.05.24.19.09.58 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 May 2016 19:09:59 -0700 (PDT) From: Wei Chen X-Google-Original-From: Wei Chen To: xen-devel@lists.xen.org Date: Wed, 25 May 2016 10:09:54 +0800 Message-Id: <1464142194-32766-1-git-send-email-Wei.Chen@linaro.org> X-Mailer: git-send-email 1.9.1 Cc: julien.grall@arm.com, sstabellini@kernel.org, Wei Chen , steve.capper@arm.com Subject: [Xen-devel] [PATCH 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Current MPIDR_HWID_MASK is using the bit definition of ARM32 MPIDR. This value is not correct while Xen is running on ARM64. Now, we add a correct value for this marco on ARM64. But this value is not a valid 64-bit immediate which can be encoded in mov instruction. So we have to use ldr to load this value to register. Signed-off-by: Wei Chen --- xen/arch/arm/arm64/head.S | 2 +- xen/include/asm-arm/processor.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index d5831f2..3090beb 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -270,7 +270,7 @@ common_start: tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */ tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */ - mov x13, #(~MPIDR_HWID_MASK) + ldr x13, =(~MPIDR_HWID_MASK) bic x24, x0, x13 /* Mask out flags to get CPU ID */ 1: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b4cce7e..284ad6a 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -18,7 +18,11 @@ #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) +#ifdef CONFIG_ARM_64 +#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) +#else #define MPIDR_HWID_MASK _AC(0xffffff,U) +#endif #define MPIDR_INVALID (~MPIDR_HWID_MASK) #define MPIDR_LEVEL_BITS (8)