From patchwork Wed Jun 22 11:15:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9192445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C12F460890 for ; Wed, 22 Jun 2016 11:17:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B19C4283E9 for ; Wed, 22 Jun 2016 11:17:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6011283F7; Wed, 22 Jun 2016 11:17:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 31CE3283EC for ; Wed, 22 Jun 2016 11:17:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFg8N-0002Rb-8z; Wed, 22 Jun 2016 11:15:51 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFg8L-0002NX-Uj for xen-devel@lists.xen.org; Wed, 22 Jun 2016 11:15:50 +0000 Received: from [193.109.254.147] by server-7.bemta-14.messagelabs.com id F7/E6-09881-5637A675; Wed, 22 Jun 2016 11:15:49 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTTelOCv coGeugcWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmjH56WXGgiXqFdvu/mFtYGxU6GLk4hAS2MQo cejtFjYI5zSjxJmT/1i7GDk52AQ0Je58/sQEYosISEtc+3yZEcRmFnCQePPxHguILSwQLtF6a hkbiM0ioCpx4/MOsDivgKvE1MunweZICMhJnDw2GczmBIqfPDoZbI6QgIvE7QN7WCcwci9gZF jFqFGcWlSWWqRraKaXVJSZnlGSm5iZo2toaKKXm1pcnJiempOYVKyXnJ+7iRHo4XoGBsYdjF9 Pex5ilORgUhLllVfOChfiS8pPqcxILM6ILyrNSS0+xCjDwaEkwXu9ACgnWJSanlqRlpkDDDWY tAQHj5IIb1AhUJq3uCAxtzgzHSJ1ilFRSpz3AEifAEgiozQPrg0W3pcYZaWEeRkZGBiEeApSi 3IzS1DlXzGKczAqCfOmgIznycwrgZv+CmgxE9DiZf3pIItLEhFSUg2MzA1lCxwdd95686dHZ+ HDjmfFD4VqXj3l+H/mSV1yZ5zy4eo/TBk3HWLruIX7nHztXI8FrjUMlNDacubVpJVRN2UkvA3 CdOMlPu3RXFN8UHp/RJDGWh7fh3v3Tp7S9q/wYfFhJpPQYrlPq6IDG13qrJY9OdgndWxuhGvR gaJ7yvyvvkrLr96jxFKckWioxVxUnAgAV7Es0moCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-7.tower-27.messagelabs.com!1466594147!44533935!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 46133 invoked from network); 22 Jun 2016 11:15:48 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-7.tower-27.messagelabs.com with SMTP; 22 Jun 2016 11:15:48 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B51E46E; Wed, 22 Jun 2016 04:16:34 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ED9B43F213; Wed, 22 Jun 2016 04:15:46 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 22 Jun 2016 12:15:26 +0100 Message-Id: <1466594130-19251-12-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466594130-19251-1-git-send-email-julien.grall@arm.com> References: <1466594130-19251-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v4 11/15] xen/arm: Detect silicon revision and set cap bits accordingly X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP After each CPU has been started, we iterate through a list of CPU errata to detect CPUs which need from hypervisor code patches. For each bug there is a function which check if that a particular CPU is affected. This needs to be done on every CPUs to cover heterogenous system properly. If a certain erratum has been detected, the capability bit will be set. In the case the erratum requires code patching, this will be triggered by the call to apply_alternatives. The code is based on the file arch/arm64/kernel/cpu_errata.c in Linux v4.6-rc3. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v4: - Add missing emacs magic blocks - Add Stefano's acked-by Changes in v3: - Move update_cpu_capabilities in a separate patch - Update the commit message to mention that workaround may not require code patching. Changes in v2: - Use XENLOG_INFO for the loglevel of the message --- xen/arch/arm/Makefile | 1 + xen/arch/arm/cpuerrata.c | 34 ++++++++++++++++++++++++++++++++++ xen/arch/arm/setup.c | 3 +++ xen/arch/arm/smpboot.c | 3 +++ xen/include/asm-arm/cpuerrata.h | 14 ++++++++++++++ xen/include/asm-arm/cpufeature.h | 6 ++++++ 6 files changed, 61 insertions(+) create mode 100644 xen/arch/arm/cpuerrata.c create mode 100644 xen/include/asm-arm/cpuerrata.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 74bd7b8..23aaf52 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -7,6 +7,7 @@ subdir-$(CONFIG_ACPI) += acpi obj-$(CONFIG_ALTERNATIVE) += alternative.o obj-y += bootfdt.o obj-y += cpu.o +obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o obj-y += device.o diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c new file mode 100644 index 0000000..03ae7b4 --- /dev/null +++ b/xen/arch/arm/cpuerrata.c @@ -0,0 +1,34 @@ +#include +#include +#include + +#define MIDR_RANGE(model, min, max) \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = min, \ + .midr_range_max = max + +static bool_t __maybe_unused +is_affected_midr_range(const struct arm_cpu_capabilities *entry) +{ + return MIDR_IS_CPU_MODEL_RANGE(boot_cpu_data.midr.bits, entry->midr_model, + entry->midr_range_min, + entry->midr_range_max); +} + +static const struct arm_cpu_capabilities arm_errata[] = { + {}, +}; + +void check_local_cpu_errata(void) +{ + update_cpu_capabilities(arm_errata, "enabled workaround for"); +} +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 97b3214..38eb888 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,8 @@ static void __init processor_id(void) } processor_setup(); + + check_local_cpu_errata(); } void dt_unreserved_regions(paddr_t s, paddr_t e, diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 3a962f7..d56b91d 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -316,6 +317,8 @@ void start_secondary(unsigned long boot_phys_offset, local_irq_enable(); local_abort_enable(); + check_local_cpu_errata(); + printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id()); startup_cpu_idle_loop(); diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h new file mode 100644 index 0000000..fe93beb --- /dev/null +++ b/xen/include/asm-arm/cpuerrata.h @@ -0,0 +1,14 @@ +#ifndef __ARM_CPUERRATA_H +#define __ARM_CPUERRATA_H + +void check_local_cpu_errata(void); + +#endif /* __ARM_CPUERRATA_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index be2414c..fb57295 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -66,6 +66,12 @@ struct arm_cpu_capabilities { const char *desc; u16 capability; bool_t (*matches)(const struct arm_cpu_capabilities *); + union { + struct { /* To be used for eratum handling only */ + u32 midr_model; + u32 midr_range_min, midr_range_max; + }; + }; }; void update_cpu_capabilities(const struct arm_cpu_capabilities *caps,