From patchwork Wed Jun 29 02:20:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luwei Kang X-Patchwork-Id: 9204223 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 62CF260752 for ; Wed, 29 Jun 2016 02:22:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5128828630 for ; Wed, 29 Jun 2016 02:22:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45C4C28635; Wed, 29 Jun 2016 02:22:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BA02B28630 for ; Wed, 29 Jun 2016 02:22:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bI56c-0002FC-HK; Wed, 29 Jun 2016 02:19:58 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bI56a-0002F6-Qe for xen-devel@lists.xen.org; Wed, 29 Jun 2016 02:19:56 +0000 Received: from [85.158.143.35] by server-2.bemta-6.messagelabs.com id 96/C9-11548-C4033775; Wed, 29 Jun 2016 02:19:56 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRWlGSWpSXmKPExsXS1tYhouttUBx u8PqTgsWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmvFt9WrmguP6FSfXHWdrYHyq2MXIySEkUCHx +NE2VhBbQoBX4siyGVC2v8ScxbcZuxg5gGoqJVatcQMJswmoS2x9vxGsRERAWuLa58tAJVwcz AKtjBI/Dk0GSwgLmErcvzaXEcRmEVCVuPtgDwuIzSvgLDFz+VcWiPlyEjfPdTJPYORewMiwil G9OLWoLLVI11AvqSgzPaMkNzEzR9fQwEwvN7W4ODE9NScxqVgvOT93EyPQtwxAsINx53OnQ4y SHExKorzn5IvDhfiS8lMqMxKLM+KLSnNSiw8xynBwKEnwftADygkWpaanVqRl5gCDDCYtwcGj JMJbCJLmLS5IzC3OTIdInWJUlBLnldAHSgiAJDJK8+DaYIF9iVFWSpiXEegQIZ6C1KLczBJU+ VeM4hyMSkAVIFN4MvNK4Ka/AlrMBLSYtTofZHFJIkJKqoHRfdUK/w6nyyaNW/craf7cnuh7Qu uQQ45F3p4KhYNuk+7OufV5NufaWw7H1qRdU1VvFvg7ZeeBhz/duHgibUJ2qLB/ml+wnl/qbqG txLOmE5LLAoMMX28+KhQ0Zeuy44FpdyZbaxbw3Xt/8JvWkpfqB7V//FD4Vl23nVV6/ca4gOVM v7gsCs81KbEUZyQaajEXFScCAOqHs49nAgAA X-Env-Sender: luwei.kang@intel.com X-Msg-Ref: server-4.tower-21.messagelabs.com!1467166794!15265142!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 41633 invoked from network); 29 Jun 2016 02:19:55 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-4.tower-21.messagelabs.com with SMTP; 29 Jun 2016 02:19:55 -0000 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 28 Jun 2016 19:19:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,543,1459839600"; d="scan'208";a="837043715" Received: from vmm-dell.bj.intel.com ([10.238.145.44]) by orsmga003.jf.intel.com with ESMTP; 28 Jun 2016 19:19:51 -0700 From: Luwei Kang To: xen-devel@lists.xen.org Date: Wed, 29 Jun 2016 10:20:04 +0800 Message-Id: <1467166804-9748-1-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 2.7.4 Cc: andrew.cooper3@citrix.com, chao.p.peng@intel.com, Luwei Kang , yong.y.wang@intel.com, jbeulich@suse.com Subject: [Xen-devel] [PATCH] x86/cpuid: AVX-512 Feature Detection X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP AVX-512 is an extention of AVX2. Its spec can be found at: https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf This patch detects AVX-512 features by CPUID. Signed-off-by: Luwei Kang --- xen/arch/x86/hvm/hvm.c | 14 ++++++++++++++ xen/arch/x86/traps.c | 22 +++++++++++++++++++++- xen/include/public/arch-x86/cpufeatureset.h | 9 +++++++++ xen/tools/gen-cpuid.py | 4 ++++ 4 files changed, 48 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index c89ab6e..7696b1e 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3474,6 +3474,20 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, xstate_sizes[_XSTATE_BNDCSR]); } + if ( _ebx & cpufeat_mask(X86_FEATURE_AVX512F) ) + { + xfeature_mask |= XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM; + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_OPMASK] + + xstate_sizes[_XSTATE_OPMASK]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_ZMM] + + xstate_sizes[_XSTATE_ZMM]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_HI_ZMM] + + xstate_sizes[_XSTATE_HI_ZMM]); + } + if ( _ecx & cpufeat_mask(X86_FEATURE_PKU) ) { xfeature_mask |= XSTATE_PKRU; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 767d0b0..8fb697b 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -975,7 +975,7 @@ void pv_cpuid(struct cpu_user_regs *regs) switch ( leaf ) { - uint32_t tmp, _ecx; + uint32_t tmp, _ecx, _ebx; case 0x00000001: c &= pv_featureset[FEATURESET_1c]; @@ -1157,6 +1157,26 @@ void pv_cpuid(struct cpu_user_regs *regs) xstate_sizes[_XSTATE_YMM]); } + if ( !is_control_domain(currd) && !is_hardware_domain(currd) ) + domain_cpuid(currd, 7, 0, &tmp, &_ebx, &tmp, &tmp); + else + cpuid_count(7, 0, &tmp, &_ebx, &tmp, &tmp); + _ebx &= pv_featureset[FEATURESET_7b0]; + + if ( _ebx & cpufeat_mask(X86_FEATURE_AVX512F) ) + { + xfeature_mask |= XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM; + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_OPMASK] + + xstate_sizes[_XSTATE_OPMASK]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_ZMM] + + xstate_sizes[_XSTATE_ZMM]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_HI_ZMM] + + xstate_sizes[_XSTATE_HI_ZMM]); + } + a = (uint32_t)xfeature_mask; d = (uint32_t)(xfeature_mask >> 32); c = xstate_size; diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 39acf8c..9320c9e 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -206,15 +206,24 @@ XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ XEN_CPUFEATURE(MPX, 5*32+14) /*S Memory Protection Extensions */ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ +XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */ +XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */ XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ +XEN_CPUFEATURE(AVX512IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */ XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */ +XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */ +XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */ XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ +XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */ +XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ +XEN_CPUFEATURE(AVX512VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */ XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 7c45eca..897e660 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -235,6 +235,10 @@ def crunch_numbers(state): # subsequent instruction groups may only be VEX encoded. AVX: [FMA, FMA4, F16C, AVX2, XOP], + # AVX-512 is an extention of AVX2 and it depends on AVX2 available. + AVX2: [AVX512F, AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD, + AVX512BW, AVX512VL, AVX512VBMI], + # CX16 is only encodable in Long Mode. LAHF_LM indicates that the # SAHF/LAHF instructions are reintroduced in Long Mode. 1GB # superpages, PCID and PKU are only available in 4 level paging.