From patchwork Tue Oct 25 03:41:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9393897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 02C6F60762 for ; Tue, 25 Oct 2016 02:36:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA3DE2927D for ; Tue, 25 Oct 2016 02:36:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DDE5229282; Tue, 25 Oct 2016 02:36:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F73F2927D for ; Tue, 25 Oct 2016 02:36:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrZA-0004dg-LU; Tue, 25 Oct 2016 02:34:16 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrZ9-0004cI-BF for xen-devel@lists.xenproject.org; Tue, 25 Oct 2016 02:34:15 +0000 Received: from [193.109.254.147] by server-5.bemta-6.messagelabs.com id 06/23-29563-6A4CE085; Tue, 25 Oct 2016 02:34:14 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsVywNykWHfZEb4 Ig+f9jBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa0bvguXMBV99K7YdsmpgPG3RxcjJISRQIbFo 22EmEFtCgFfiyLIZrBB2gMShrQuA4lxANQ2MEv9aJ4Al2ATUJR5/7QFrEBFQkri3ajJYEbPAf kaJXy8fs4AkhAUsJa6dPcoOYrMIqErsebwMrIFXwENi3YrzjBAb5CROHpsMNpQTKH5n73F2iI vcJfoamhgnMPIuYGRYxahRnFpUllqka2iul1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5y fu4kRGA4MQLCD8fbGgEOMkhxMSqK8MzfxRQjxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4F1/GCgn WJSanlqRlpkDDEyYtAQHj5II7xOQNG9xQWJucWY6ROoUo6KUOO8ikIQASCKjNA+uDRYNlxhlp YR5GYEOEeIpSC3KzSxBlX/FKM7BqCTM+wJkCk9mXgnc9FdAi5mAFgvG84AsLklESEk1MDI5eR b/UvlUEmb3KP6YxWsvtjd51w58//TBOEnB/K5eWfARQYdLi3u+CtY7PMlYlvtGQNbgw2eOa+X 1c3LrLyw33jJdYutST9VlGayfWtWY1m/jXC6u8+nxf+u9boq9el/6jq4vFmuV7/Bx+tX+TLI9 691Slagld7c5Pby7JiXqtd0j5YdbOZVYijMSDbWYi4oTAeEctuaBAgAA X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1477362814!54875270!13 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.13; banners=-,-,- X-VirusChecked: Checked Received: (qmail 60996 invoked from network); 25 Oct 2016 02:34:13 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-14.tower-27.messagelabs.com with DHE-RSA-CAMELLIA256-SHA encrypted SMTP; 25 Oct 2016 02:34:13 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 24 Oct 2016 19:34:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,544,1473145200"; d="scan'208"; a="1049570237" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.60]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2016 19:34:11 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Tue, 25 Oct 2016 11:41:00 +0800 Message-Id: <1477366863-5246-13-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> References: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> Cc: wei.liu2@citrix.com, he.chen@linux.intel.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, Yi Sun , jbeulich@suse.com, chao.p.peng@linux.intel.com Subject: [Xen-devel] [PATCH v3 12/15] x86: Implement L2 CAT in psr.c. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable L2 CAT (Cache Allocation Technology) feature support in psr.c. - Implement 'struct feat_ops' callback functions for L2 CAT. - Initialize L2 CAT feature and add it into feature list to enable L2 CAT in psr.c. - Free resources when CPU dead or cancelled. Signed-off-by: He Chen Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 230 +++++++++++++++++++++++++++++++++++++++- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 + 3 files changed, 229 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 32f899a..c6f57c0 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -31,9 +31,13 @@ #define COS_MAX 1 #define CDP_FLAG 2 +#define CAT_CBM_LEN_MASK 0x1f +#define CAT_COS_MAX_MASK 0xffff + enum psr_feat_type { PSR_SOCKET_L3_CAT = 0, PSR_SOCKET_L3_CDP, + PSR_SOCKET_L2_CAT, }; struct feat_node; @@ -161,7 +165,10 @@ struct feat_node { }; struct psr_cat_socket_info { - /* bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP */ + /* + * bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP + * bit 2: L2 CAT + */ unsigned int feat_mask; unsigned int nr_feat; struct list_head feat_list; @@ -204,8 +211,9 @@ static unsigned int __read_mostly opt_cos_max = MAX_COS_REG_NUM - 1; static uint64_t rmid_mask; static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); -/* Feature list entry of feature L3 CAT/CDP. */ +/* Declare feature list entry. */ static struct feat_node *feat_l3; +static struct feat_node *feat_l2; /* Common functions. */ static void free_feature(struct psr_cat_socket_info *info) @@ -228,6 +236,12 @@ static void free_feature(struct psr_cat_socket_info *info) xfree(feat_l3); feat_l3 = NULL; } + + if ( feat_l2 ) + { + xfree(feat_l2); + feat_l2 = NULL; + } } static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm) @@ -253,6 +267,194 @@ static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm) return 1; } +/* L2 CAT callback functions implementation. */ +static void l2_cat_init_feature(unsigned int eax, unsigned int ebx, + unsigned int ecx, unsigned int edx, + struct feat_node *feat, + struct psr_cat_socket_info *info) +{ + struct psr_cat_hw_info l2_cat; + unsigned int socket; + + /* No valid values so do not enable the feature. */ + if ( !eax || !edx ) + return; + + l2_cat.cbm_len = (eax & CAT_CBM_LEN_MASK) + 1; + l2_cat.cos_max = min(opt_cos_max, edx & CAT_COS_MAX_MASK); + + /* cos=0 is reserved as default cbm(all ones). */ + feat->cos_reg_val[0] = (1ull << l2_cat.cbm_len) - 1; + + feat->feature = PSR_SOCKET_L2_CAT; + __set_bit(PSR_SOCKET_L2_CAT, &info->feat_mask); + + feat->info = l2_cat; + + info->nr_feat++; + + /* Add this feature into list. */ + list_add_tail(&feat->list, &info->feat_list); + + socket = cpu_to_socket(smp_processor_id()); + printk(XENLOG_INFO "L2 CAT: enabled on socket %u, cos_max:%u, cbm_len:%u.\n", + socket, feat->info.cos_max, feat->info.cbm_len); +} + +static bool l2_cat_get_feat_info(const struct feat_node *feat, + enum cbm_type type, + uint32_t dat[], uint32_t array_len) +{ + if ( type != PSR_CBM_TYPE_L2 || !dat || 2 > array_len ) + return false; + + dat[CBM_LEN] = feat->info.cbm_len; + dat[COS_MAX] = feat->info.cos_max; + + return true; +} + +static int l2_cat_get_val(const struct feat_node *feat, unsigned int cos, + enum cbm_type type, uint64_t *val) +{ + if ( type != PSR_CBM_TYPE_L2 ) + return 0; + + if ( cos > feat->info.cos_max ) + cos = 0; + + /* L2 CAT */ + *val = feat->cos_reg_val[cos]; + + return 1; +} + +static unsigned int l2_cat_get_max_cos_max(const struct feat_node *feat) +{ + return feat->info.cos_max; +} + +static unsigned int l2_cat_get_cos_num(const struct feat_node *feat) +{ + /* L2 CAT uses one COS. */ + return 1; +} + +static int l2_cat_get_old_val(uint64_t val[], + const struct feat_node *feat, + unsigned int old_cos) +{ + if ( old_cos > feat->info.cos_max ) + /* Use default value. */ + old_cos = 0; + + val[0] = feat->cos_reg_val[old_cos]; + + /* L2 CAT uses one COS. */ + return 1; +} + +static int l2_cat_set_new_val(uint64_t val[], + const struct feat_node *feat, + unsigned int old_cos, + enum cbm_type type, + uint64_t m) +{ + if ( type == PSR_CBM_TYPE_L2 ) + { + if ( !psr_check_cbm(feat->info.cbm_len, m) ) + return -EINVAL; + + val[0] = m; + } + + /* L2 CAT uses one COS. */ + return 1; +} + +static int l2_cat_compare_val(const uint64_t val[], + const struct feat_node *feat, + unsigned int cos, bool *found) +{ + uint64_t l2_def_cbm; + + l2_def_cbm = (1ull << feat->info.cbm_len) - 1; + + /* L2 CAT */ + if ( cos > feat->info.cos_max ) + { + if ( val[0] != l2_def_cbm ) + { + *found = false; + return -ENOENT; + } + *found = true; + } + else + *found = (val[0] == feat->cos_reg_val[cos]); + + /* L2 CAT uses one COS. */ + return 1; +} + +static unsigned int l2_cat_get_cos_max_from_type(const struct feat_node *feat, + enum cbm_type type) +{ + if ( type != PSR_CBM_TYPE_L2 ) + return 0; + + return feat->info.cos_max; +} + +static unsigned int l2_cat_exceeds_cos_max(const uint64_t val[], + const struct feat_node *feat, + unsigned int cos) +{ + uint64_t l2_def_cbm; + + l2_def_cbm = (1ull << feat->info.cbm_len) - 1; + + /* L2 CAT */ + if ( cos > feat->info.cos_max && + val[0] != l2_def_cbm ) + /* + * Exceed cos_max and value to set is not default, + * return error. + */ + return 0; + + /* L2 CAT uses one COS. */ + return 1; +} + +static int l2_cat_write_msr(unsigned int cos, const uint64_t val[], + struct feat_node *feat) +{ + /* L2 CAT */ + if ( cos > feat->info.cos_max ) + return 1; + + feat->cos_reg_val[cos] = val[0]; + wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val[0]); + + /* L2 CAT uses one COS. */ + return 1; +} + +struct feat_ops l2_cat_ops = { + .init_feature = l2_cat_init_feature, + .get_feat_info = l2_cat_get_feat_info, + .get_val = l2_cat_get_val, + .get_max_cos_max = l2_cat_get_max_cos_max, + .get_cos_num = l2_cat_get_cos_num, + .get_old_val = l2_cat_get_old_val, + .set_new_val = l2_cat_set_new_val, + .compare_val = l2_cat_compare_val, + .get_cos_max_from_type = l2_cat_get_cos_max_from_type, + .exceeds_cos_max = l2_cat_exceeds_cos_max, + .write_msr = l2_cat_write_msr, +}; + /* L3 CAT/CDP callback functions implementation. */ static void l3_cat_init_feature(unsigned int eax, unsigned int ebx, unsigned int ecx, unsigned int edx, @@ -267,8 +469,8 @@ static void l3_cat_init_feature(unsigned int eax, unsigned int ebx, if ( !eax || !edx ) return; - l3_cat.cbm_len = (eax & 0x1f) + 1; - l3_cat.cos_max = min(opt_cos_max, edx & 0xffff); + l3_cat.cbm_len = (eax & CAT_CBM_LEN_MASK) + 1; + l3_cat.cos_max = min(opt_cos_max, edx & CAT_COS_MAX_MASK); /* cos=0 is reserved as default cbm(all ones). */ feat->cos_reg_val[0] = (1ull << l3_cat.cbm_len) - 1; @@ -1246,6 +1448,14 @@ static int cat_cpu_prepare(unsigned int cpu) (feat_l3 = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2 == NULL && + (feat_l2 = xzalloc(struct feat_node)) == NULL ) + { + xfree(feat_l3); + feat_l3 = NULL; + return -ENOMEM; + } + return 0; } @@ -1278,6 +1488,18 @@ static void cat_cpu_init(void) feat_tmp->ops = l3_cat_ops; feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info); } + + cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx); + if ( ebx & PSR_RESOURCE_TYPE_L2 ) + { + feat_tmp = feat_l2; + feat_l2 = NULL; + + /* Initialize L2 CAT according to CPUID. */ + cpuid_count(PSR_CPUID_LEVEL_CAT, 2, &eax, &ebx, &ecx, &edx); + feat_tmp->ops = l2_cat_ops; + feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info); + } } static void cat_cpu_fini(unsigned int cpu) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 98dbff1..a41e63a 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -343,6 +343,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index 17ee6f3..37ad185 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -50,6 +51,7 @@ enum cbm_type { PSR_CBM_TYPE_L3, PSR_CBM_TYPE_L3_CODE, PSR_CBM_TYPE_L3_DATA, + PSR_CBM_TYPE_L2, }; extern struct psr_cmt *psr_cmt;