diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 32f899a..c6f57c0 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -31,9 +31,13 @@
 #define COS_MAX  1
 #define CDP_FLAG 2
 
+#define CAT_CBM_LEN_MASK 0x1f
+#define CAT_COS_MAX_MASK 0xffff
+
 enum psr_feat_type {
     PSR_SOCKET_L3_CAT = 0,
     PSR_SOCKET_L3_CDP,
+    PSR_SOCKET_L2_CAT,
 };
 
 struct feat_node;
@@ -161,7 +165,10 @@ struct feat_node {
 };
 
 struct psr_cat_socket_info {
-    /* bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP */
+    /*
+     * bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP
+     * bit 2:   L2 CAT
+     */
     unsigned int feat_mask;
     unsigned int nr_feat;
     struct list_head feat_list;
@@ -204,8 +211,9 @@ static unsigned int __read_mostly opt_cos_max = MAX_COS_REG_NUM - 1;
 static uint64_t rmid_mask;
 static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
 
-/* Feature list entry of feature L3 CAT/CDP. */
+/* Declare feature list entry. */
 static struct feat_node *feat_l3;
+static struct feat_node *feat_l2;
 
 /* Common functions. */
 static void free_feature(struct psr_cat_socket_info *info)
@@ -228,6 +236,12 @@ static void free_feature(struct psr_cat_socket_info *info)
         xfree(feat_l3);
         feat_l3 = NULL;
     }
+
+    if ( feat_l2 )
+    {
+        xfree(feat_l2);
+        feat_l2 = NULL;
+    }
 }
 
 static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
@@ -253,6 +267,194 @@ static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
     return 1;
 }
 
+/* L2 CAT callback functions implementation. */
+static void l2_cat_init_feature(unsigned int eax, unsigned int ebx,
+                                unsigned int ecx, unsigned int edx,
+                                struct feat_node *feat,
+                                struct psr_cat_socket_info *info)
+{
+    struct psr_cat_hw_info l2_cat;
+    unsigned int socket;
+
+    /* No valid values so do not enable the feature. */
+    if ( !eax || !edx )
+        return;
+
+    l2_cat.cbm_len = (eax & CAT_CBM_LEN_MASK) + 1;
+    l2_cat.cos_max = min(opt_cos_max, edx & CAT_COS_MAX_MASK);
+
+    /* cos=0 is reserved as default cbm(all ones). */
+    feat->cos_reg_val[0] = (1ull << l2_cat.cbm_len) - 1;
+
+    feat->feature = PSR_SOCKET_L2_CAT;
+    __set_bit(PSR_SOCKET_L2_CAT, &info->feat_mask);
+
+    feat->info = l2_cat;
+
+    info->nr_feat++;
+
+    /* Add this feature into list. */
+    list_add_tail(&feat->list, &info->feat_list);
+
+    socket = cpu_to_socket(smp_processor_id());
+    printk(XENLOG_INFO "L2 CAT: enabled on socket %u, cos_max:%u, cbm_len:%u.\n",
+           socket, feat->info.cos_max, feat->info.cbm_len);
+}
+
+static bool l2_cat_get_feat_info(const struct feat_node *feat,
+                                 enum cbm_type type,
+                                 uint32_t dat[], uint32_t array_len)
+{
+    if ( type != PSR_CBM_TYPE_L2 || !dat || 2 > array_len )
+        return false;
+
+    dat[CBM_LEN] = feat->info.cbm_len;
+    dat[COS_MAX] = feat->info.cos_max;
+
+    return true;
+}
+
+static int l2_cat_get_val(const struct feat_node *feat, unsigned int cos,
+                          enum cbm_type type, uint64_t *val)
+{
+    if ( type != PSR_CBM_TYPE_L2 )
+         return 0;
+
+    if ( cos > feat->info.cos_max )
+        cos = 0;
+
+    /* L2 CAT */
+    *val =  feat->cos_reg_val[cos];
+
+    return 1;
+}
+
+static unsigned int l2_cat_get_max_cos_max(const struct feat_node *feat)
+{
+    return feat->info.cos_max;
+}
+
+static unsigned int l2_cat_get_cos_num(const struct feat_node *feat)
+{
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static int l2_cat_get_old_val(uint64_t val[],
+                              const struct feat_node *feat,
+                              unsigned int old_cos)
+{
+    if ( old_cos > feat->info.cos_max )
+        /* Use default value. */
+        old_cos = 0;
+
+    val[0] = feat->cos_reg_val[old_cos];
+
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static int l2_cat_set_new_val(uint64_t val[],
+                              const struct feat_node *feat,
+                              unsigned int old_cos,
+                              enum cbm_type type,
+                              uint64_t m)
+{
+    if ( type == PSR_CBM_TYPE_L2 )
+    {
+        if ( !psr_check_cbm(feat->info.cbm_len, m) )
+            return -EINVAL;
+
+        val[0] = m;
+    }
+
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static int l2_cat_compare_val(const uint64_t val[],
+                              const struct feat_node *feat,
+                              unsigned int cos, bool *found)
+{
+    uint64_t l2_def_cbm;
+
+    l2_def_cbm = (1ull << feat->info.cbm_len) - 1;
+
+    /* L2 CAT */
+    if ( cos > feat->info.cos_max )
+    {
+        if ( val[0] != l2_def_cbm )
+        {
+            *found = false;
+            return -ENOENT;
+        }
+        *found = true;
+    }
+    else
+        *found = (val[0] == feat->cos_reg_val[cos]);
+
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static unsigned int l2_cat_get_cos_max_from_type(const struct feat_node *feat,
+                                                 enum cbm_type type)
+{
+    if ( type != PSR_CBM_TYPE_L2 )
+        return 0;
+
+    return feat->info.cos_max;
+}
+
+static unsigned int l2_cat_exceeds_cos_max(const uint64_t val[],
+                                           const struct feat_node *feat,
+                                           unsigned int cos)
+{
+    uint64_t l2_def_cbm;
+
+    l2_def_cbm = (1ull << feat->info.cbm_len) - 1;
+
+    /* L2 CAT */
+    if ( cos > feat->info.cos_max &&
+         val[0] != l2_def_cbm )
+            /*
+             * Exceed cos_max and value to set is not default,
+             * return error.
+             */
+            return 0;
+
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+static int l2_cat_write_msr(unsigned int cos, const uint64_t val[],
+                            struct feat_node *feat)
+{
+    /* L2 CAT */
+    if ( cos > feat->info.cos_max )
+        return 1;
+
+    feat->cos_reg_val[cos] = val[0];
+    wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val[0]);
+
+    /* L2 CAT uses one COS. */
+    return 1;
+}
+
+struct feat_ops l2_cat_ops = {
+    .init_feature = l2_cat_init_feature,
+    .get_feat_info = l2_cat_get_feat_info,
+    .get_val = l2_cat_get_val,
+    .get_max_cos_max = l2_cat_get_max_cos_max,
+    .get_cos_num = l2_cat_get_cos_num,
+    .get_old_val = l2_cat_get_old_val,
+    .set_new_val = l2_cat_set_new_val,
+    .compare_val = l2_cat_compare_val,
+    .get_cos_max_from_type = l2_cat_get_cos_max_from_type,
+    .exceeds_cos_max = l2_cat_exceeds_cos_max,
+    .write_msr = l2_cat_write_msr,
+};
+
 /* L3 CAT/CDP callback functions implementation. */
 static void l3_cat_init_feature(unsigned int eax, unsigned int ebx,
                                 unsigned int ecx, unsigned int edx,
@@ -267,8 +469,8 @@ static void l3_cat_init_feature(unsigned int eax, unsigned int ebx,
     if ( !eax || !edx )
         return;
 
-    l3_cat.cbm_len = (eax & 0x1f) + 1;
-    l3_cat.cos_max = min(opt_cos_max, edx & 0xffff);
+    l3_cat.cbm_len = (eax & CAT_CBM_LEN_MASK) + 1;
+    l3_cat.cos_max = min(opt_cos_max, edx & CAT_COS_MAX_MASK);
 
     /* cos=0 is reserved as default cbm(all ones). */
     feat->cos_reg_val[0] = (1ull << l3_cat.cbm_len) - 1;
@@ -1246,6 +1448,14 @@ static int cat_cpu_prepare(unsigned int cpu)
          (feat_l3 = xzalloc(struct feat_node)) == NULL )
         return -ENOMEM;
 
+    if ( feat_l2 == NULL &&
+         (feat_l2 = xzalloc(struct feat_node)) == NULL )
+    {
+        xfree(feat_l3);
+        feat_l3 = NULL;
+        return -ENOMEM;
+    }
+
     return 0;
 }
 
@@ -1278,6 +1488,18 @@ static void cat_cpu_init(void)
         feat_tmp->ops = l3_cat_ops;
         feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info);
     }
+
+    cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
+    if ( ebx & PSR_RESOURCE_TYPE_L2 )
+    {
+        feat_tmp = feat_l2;
+        feat_l2 = NULL;
+
+        /* Initialize L2 CAT according to CPUID. */
+        cpuid_count(PSR_CPUID_LEVEL_CAT, 2, &eax, &ebx, &ecx, &edx);
+        feat_tmp->ops = l2_cat_ops;
+        feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info);
+    }
 }
 
 static void cat_cpu_fini(unsigned int cpu)
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 98dbff1..a41e63a 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -343,6 +343,7 @@
 #define MSR_IA32_PSR_L3_MASK(n)	(0x00000c90 + (n))
 #define MSR_IA32_PSR_L3_MASK_CODE(n)	(0x00000c90 + (n) * 2 + 1)
 #define MSR_IA32_PSR_L3_MASK_DATA(n)	(0x00000c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n)		(0x00000d10 + (n))
 
 /* Intel Model 6 */
 #define MSR_P6_PERFCTR(n)		(0x000000c1 + (n))
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 17ee6f3..37ad185 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -23,6 +23,7 @@
 
 /* Resource Type Enumeration */
 #define PSR_RESOURCE_TYPE_L3            0x2
+#define PSR_RESOURCE_TYPE_L2            0x4
 
 /* L3 Monitoring Features */
 #define PSR_CMT_L3_OCCUPANCY           0x1
@@ -50,6 +51,7 @@ enum cbm_type {
     PSR_CBM_TYPE_L3,
     PSR_CBM_TYPE_L3_CODE,
     PSR_CBM_TYPE_L3_DATA,
+    PSR_CBM_TYPE_L2,
 };
 
 extern struct psr_cmt *psr_cmt;
