@@ -17,6 +17,7 @@
#include <xen/cpu.h>
#include <xen/err.h>
#include <xen/sched.h>
+#include <xen/list.h>
#include <asm/psr.h>
#define PSR_CMT (1<<0)
@@ -26,8 +27,10 @@
/* Per spec, the maximum COS register number is 128. */
#define MAX_COS_REG_NUM 128
-#define PSR_SOCKET_L3_CAT 0
-#define PSR_SOCKET_L3_CDP 1
+enum psr_feat_type {
+ PSR_SOCKET_L3_CAT = 0,
+ PSR_SOCKET_L3_CDP,
+};
/* CAT/CDP HW info data structure. */
struct psr_cat_hw_info {
@@ -35,16 +38,25 @@ struct psr_cat_hw_info {
unsigned int cos_max;
};
-struct psr_cat_socket_info {
- /* bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP */
- unsigned int feat_mask;
- struct psr_cat_hw_info l3_info;
+struct feat_node {
+ /* Which feature it is. */
+ enum psr_feat_type feature;
+ /* Feature HW info. */
+ struct psr_cat_hw_info info;
/*
* Store the values of COS registers:
* CAT uses 1 entry for one COS ID;
* CDP uses 2 entries for one COS ID and DATA is the first one.
*/
uint64_t cos_reg_val[MAX_COS_REG_NUM];
+ struct list_head list;
+};
+
+struct psr_cat_socket_info {
+ /* bit 1~0: [01]->L3 CAT-only, [10]->L3 CDP */
+ unsigned int feat_mask;
+ unsigned int nr_feat;
+ struct list_head feat_list;
/*
* Every entry of cos_ref is the reference count of a COS register.
* One entry of cos_ref corresponds to one COS ID.
@@ -56,18 +68,18 @@ struct psr_cat_socket_info {
/*
* get_data - get DATA COS register value from input COS ID.
- * @info: the struct psr_cat_socket_info pointer.
+ * @feat: the feature list entry.
* @cos: the COS ID.
*/
-#define get_cdp_data(info, cos) \
- info->cos_reg_val[cos * 2]
+#define get_cdp_data(feat, cos) \
+ feat->cos_reg_val[cos * 2]
/*
* get_cdp_code - get CODE COS register value from input COS ID.
- * @info: the struct psr_cat_socket_info pointer.
+ * @feat: the feature list entry.
* @cos: the COS ID.
*/
-#define get_cdp_code(info, cos) \
- info->cos_reg_val[cos * 2 + 1]
+#define get_cdp_code(feat, cos) \
+ feat->cos_reg_val[cos * 2 + 1]
struct psr_assoc {
uint64_t val;
@@ -84,6 +96,43 @@ static unsigned int __read_mostly opt_cos_max = MAX_COS_REG_NUM - 1;
static uint64_t rmid_mask;
static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
+/* Feature list entry of feature L3 CAT/CDP. */
+static struct feat_node *feat_l3;
+
+static struct feat_node *get_feat_l3(struct psr_cat_socket_info *info)
+{
+ struct feat_node *feat_tmp;
+
+ list_for_each_entry(feat_tmp, &info->feat_list, list)
+ if ( feat_tmp->feature == PSR_SOCKET_L3_CAT ||
+ feat_tmp->feature == PSR_SOCKET_L3_CDP )
+ return feat_tmp;
+
+ return NULL;
+}
+
+static void free_feature(struct psr_cat_socket_info *info)
+{
+ struct feat_node *feat_tmp;
+
+ if ( !info )
+ return;
+
+ list_for_each_entry(feat_tmp, &info->feat_list, list)
+ {
+ clear_bit(feat_tmp->feature, &info->feat_mask);
+ list_del(&feat_tmp->list);
+ xfree(feat_tmp);
+ }
+
+ /* Free feature which are not added into feat_list. */
+ if ( feat_l3 )
+ {
+ xfree(feat_l3);
+ feat_l3 = NULL;
+ }
+}
+
static unsigned int get_socket_cpu(unsigned int socket)
{
if ( likely(socket < nr_sockets) )
@@ -240,10 +289,16 @@ static inline void psr_assoc_init(void)
if ( cat_socket_info )
{
unsigned int socket = cpu_to_socket(smp_processor_id());
+ struct psr_cat_socket_info *info = cat_socket_info + socket;
+ struct feat_node *feat_tmp;
+
+ feat_tmp = get_feat_l3(info);
+ if ( !feat_tmp )
+ return;
- if ( cat_socket_info[socket].feat_mask )
+ if ( info->feat_mask )
psra->cos_mask = ((1ull << get_count_order(
- cat_socket_info[socket].l3_info.cos_max)) - 1) << 32;
+ feat_tmp->info.cos_max)) - 1) << 32;
}
if ( psr_cmt_enabled() || psra->cos_mask )
@@ -303,12 +358,17 @@ int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
uint32_t *cos_max, uint32_t *flags)
{
struct psr_cat_socket_info *info = get_cat_socket_info(socket);
+ struct feat_node *feat_tmp;
if ( IS_ERR(info) )
return PTR_ERR(info);
- *cbm_len = info->l3_info.cbm_len;
- *cos_max = info->l3_info.cos_max;
+ feat_tmp = get_feat_l3(info);
+ if ( !feat_tmp )
+ return -ENOENT;
+
+ *cbm_len = feat_tmp->info.cbm_len;
+ *cos_max = feat_tmp->info.cos_max;
*flags = 0;
if ( cdp_is_enabled(socket) )
@@ -323,30 +383,35 @@ int psr_get_l3_cbm(struct domain *d, unsigned int socket,
struct psr_cat_socket_info *info = get_cat_socket_info(socket);
bool_t cdp_enabled = cdp_is_enabled(socket);
unsigned int cos = d->arch.psr_cos_ids[socket];
+ struct feat_node *feat_tmp;
if ( IS_ERR(info) )
return PTR_ERR(info);
+ feat_tmp = get_feat_l3(info);
+ if ( !feat_tmp )
+ return -ENOENT;
+
switch ( type )
{
case PSR_CBM_TYPE_L3:
if ( cdp_enabled )
return -EXDEV;
- *cbm = info->cos_reg_val[cos];
+ *cbm = feat_tmp->cos_reg_val[cos];
break;
case PSR_CBM_TYPE_L3_CODE:
if ( !cdp_enabled )
- *cbm = info->cos_reg_val[cos];
+ *cbm = feat_tmp->cos_reg_val[cos];
else
- *cbm = get_cdp_code(info, cos);
+ *cbm = get_cdp_code(feat_tmp, cos);
break;
case PSR_CBM_TYPE_L3_DATA:
if ( !cdp_enabled )
- *cbm = info->cos_reg_val[cos];
+ *cbm = feat_tmp->cos_reg_val[cos];
else
- *cbm = get_cdp_data(info, cos);
+ *cbm = get_cdp_data(feat_tmp, cos);
break;
default:
@@ -425,7 +490,7 @@ static int write_l3_cbm(unsigned int socket, unsigned int cos,
return 0;
}
-static int find_cos(struct psr_cat_socket_info *info, unsigned int *ref,
+static int find_cos(struct feat_node *feat, unsigned int *ref,
unsigned int cos_max,
uint64_t cbm_code, uint64_t cbm_data, bool_t cdp_enabled)
{
@@ -434,9 +499,9 @@ static int find_cos(struct psr_cat_socket_info *info, unsigned int *ref,
for ( cos = 0; cos <= cos_max; cos++ )
{
if ( (ref[cos] || cos == 0) &&
- ((!cdp_enabled && info->cos_reg_val[cos] == cbm_code) ||
- (cdp_enabled && get_cdp_code(info, cos) == cbm_code &&
- get_cdp_data(info, cos) == cbm_data)) )
+ ((!cdp_enabled && feat->cos_reg_val[cos] == cbm_code) ||
+ (cdp_enabled && get_cdp_code(feat, cos) == cbm_code &&
+ get_cdp_data(feat, cos) == cbm_data)) )
return cos;
}
@@ -469,18 +534,23 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
bool_t cdp_enabled = cdp_is_enabled(socket);
struct psr_cat_socket_info *info = get_cat_socket_info(socket);
unsigned int *ref;
+ struct feat_node *feat_tmp;
if ( IS_ERR(info) )
return PTR_ERR(info);
- if ( !psr_check_cbm(info->l3_info.cbm_len, cbm) )
+ feat_tmp = get_feat_l3(info);
+ if ( !feat_tmp )
+ return -ENOENT;
+
+ if ( !psr_check_cbm(feat_tmp->info.cbm_len, cbm) )
return -EINVAL;
if ( !cdp_enabled && (type == PSR_CBM_TYPE_L3_CODE ||
type == PSR_CBM_TYPE_L3_DATA) )
return -ENXIO;
- cos_max = info->l3_info.cos_max;
+ cos_max = feat_tmp->info.cos_max;
old_cos = d->arch.psr_cos_ids[socket];
ref = info->cos_ref;
@@ -493,11 +563,11 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
case PSR_CBM_TYPE_L3_CODE:
cbm_code = cbm;
- cbm_data = get_cdp_data(info, old_cos);
+ cbm_data = get_cdp_data(feat_tmp, old_cos);
break;
case PSR_CBM_TYPE_L3_DATA:
- cbm_code = get_cdp_code(info, old_cos);
+ cbm_code = get_cdp_code(feat_tmp, old_cos);
cbm_data = cbm;
break;
@@ -507,7 +577,7 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
}
spin_lock(&info->ref_lock);
- cos = find_cos(info, ref, cos_max, cbm_code, cbm_data, cdp_enabled);
+ cos = find_cos(feat_tmp, ref, cos_max, cbm_code, cbm_data, cdp_enabled);
if ( cos >= 0 )
{
if ( cos == old_cos )
@@ -527,9 +597,9 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
/* We try to avoid writing MSR. */
if ( (cdp_enabled &&
- (get_cdp_code(info, cos) != cbm_code ||
- get_cdp_data(info, cos) != cbm_data)) ||
- (!cdp_enabled && info->cos_reg_val[cos] != cbm_code) )
+ (get_cdp_code(feat_tmp, cos) != cbm_code ||
+ get_cdp_data(feat_tmp, cos) != cbm_data)) ||
+ (!cdp_enabled && feat_tmp->cos_reg_val[cos] != cbm_code) )
{
ret = write_l3_cbm(socket, cos, cbm_code, cbm_data, cdp_enabled);
if ( ret )
@@ -537,8 +607,8 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
spin_unlock(&info->ref_lock);
return ret;
}
- get_cdp_code(info, cos) = cbm_code;
- get_cdp_data(info, cos) = cbm_data;
+ get_cdp_code(feat_tmp, cos) = cbm_code;
+ get_cdp_data(feat_tmp, cos) = cbm_data;
}
}
@@ -599,7 +669,10 @@ static int cat_cpu_prepare(unsigned int cpu)
if ( !cat_socket_info )
return 0;
- /* Keep this function for future usage. */
+ /* Malloc memory for the global feature head here. */
+ if ( feat_l3 == NULL &&
+ (feat_l3 = xzalloc(struct feat_node)) == NULL )
+ return -ENOMEM;
return 0;
}
@@ -612,6 +685,7 @@ static void cat_cpu_init(void)
unsigned int cpu = smp_processor_id();
uint64_t val;
const struct cpuinfo_x86 *c = cpu_data + cpu;
+ struct feat_node *feat_tmp;
if ( !cpu_has(c, X86_FEATURE_PQE) || c->cpuid_level < PSR_CPUID_LEVEL_CAT )
return;
@@ -624,12 +698,15 @@ static void cat_cpu_init(void)
cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
if ( ebx & PSR_RESOURCE_TYPE_L3 )
{
+ feat_tmp = feat_l3;
+ feat_l3 = NULL;
+
cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &ecx, &edx);
- info->l3_info.cbm_len = (eax & 0x1f) + 1;
- info->l3_info.cos_max = min(opt_cos_max, edx & 0xffff);
+ feat_tmp->info.cbm_len = (eax & 0x1f) + 1;
+ feat_tmp->info.cos_max = min(opt_cos_max, edx & 0xffff);
/* cos=0 is reserved as default cbm(all ones). */
- info->cos_reg_val[0] = (1ull << info->l3_info.cbm_len) - 1;
+ feat_tmp->cos_reg_val[0] = (1ull << feat_tmp->info.cbm_len) - 1;
spin_lock_init(&info->ref_lock);
@@ -637,26 +714,31 @@ static void cat_cpu_init(void)
!test_bit(PSR_SOCKET_L3_CDP, &info->feat_mask) )
{
/* CODE */
- get_cdp_code(info, 0) = (1ull << info->l3_info.cbm_len) - 1;
+ get_cdp_code(feat_tmp, 0) = (1ull << feat_tmp->info.cbm_len) - 1;
/* DATA */
- get_cdp_data(info, 0) = (1ull << info->l3_info.cbm_len) - 1;
+ get_cdp_data(feat_tmp, 0) = (1ull << feat_tmp->info.cbm_len) - 1;
/* We only write mask1 since mask0 is always all ones by default. */
- wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << info->l3_info.cbm_len) - 1);
+ wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << feat_tmp->info.cbm_len) - 1);
rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT));
/* Cut half of cos_max when CDP is enabled. */
- info->l3_info.cos_max >>= 1;
+ feat_tmp->info.cos_max >>= 1;
__set_bit(PSR_SOCKET_L3_CDP, &info->feat_mask);
- }
- else
+ } else {
+ feat_tmp->feature = PSR_SOCKET_L3_CAT;
__set_bit(PSR_SOCKET_L3_CAT, &info->feat_mask);
+ }
+
+ info->nr_feat++;
+ /* Add this feature into list. */
+ list_add_tail(&feat_tmp->list, &info->feat_list);
printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u, CDP:%s\n",
- socket, info->l3_info.cos_max, info->l3_info.cbm_len,
+ socket, feat_tmp->info.cos_max, feat_tmp->info.cbm_len,
cdp_is_enabled(socket) ? "on" : "off");
}
}
@@ -669,21 +751,25 @@ static void cat_cpu_fini(unsigned int cpu)
{
struct psr_cat_socket_info *info = cat_socket_info + socket;
- if ( cdp_is_enabled(socket) )
- clear_bit(PSR_SOCKET_L3_CDP, &info->feat_mask);
- else
- clear_bit(PSR_SOCKET_L3_CAT, &info->feat_mask);
+ free_feature(info);
}
}
static void __init psr_cat_free(void)
{
+ unsigned int i;
+
+ for ( i = 0; i < nr_sockets; i++ )
+ free_feature(&cat_socket_info[i]);
+
xfree(cat_socket_info);
cat_socket_info = NULL;
}
static void __init init_psr_cat(void)
{
+ unsigned int i;
+
if ( opt_cos_max < 1 )
{
printk(XENLOG_INFO "CAT: disabled, cos_max is too small\n");
@@ -693,7 +779,13 @@ static void __init init_psr_cat(void)
cat_socket_info = xzalloc_array(struct psr_cat_socket_info, nr_sockets);
if ( !cat_socket_info )
+ {
printk(XENLOG_INFO "Fail to alloc socket_info!\n");
+ return;
+ }
+
+ for ( i = 0; i < nr_sockets; i++ )
+ INIT_LIST_HEAD(&cat_socket_info[i].feat_list);
}
static int psr_cpu_prepare(unsigned int cpu)
This patch creates a feature list to manage features enabled on socket. A feature list entry contains the feature's info, including which feature it is, the feature HW info and the COS registers values. So far, only is L3 CAT/CDP added into list. So, the operations are L3 CAT/CDP specific. The universal operations will be abstracted and implemented in following patches. Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> --- xen/arch/x86/psr.c | 192 +++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 142 insertions(+), 50 deletions(-)