From patchwork Tue Oct 25 03:40:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9393885 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF3B060762 for ; Tue, 25 Oct 2016 02:36:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C2FA928A62 for ; Tue, 25 Oct 2016 02:36:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B6D702927F; Tue, 25 Oct 2016 02:36:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3B3F328A62 for ; Tue, 25 Oct 2016 02:36:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrYv-0004PM-5w; Tue, 25 Oct 2016 02:34:01 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrYt-0004MO-V7 for xen-devel@lists.xenproject.org; Tue, 25 Oct 2016 02:34:00 +0000 Received: from [193.109.254.147] by server-10.bemta-6.messagelabs.com id 92/39-21986-794CE085; Tue, 25 Oct 2016 02:33:59 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRWlGSWpSXmKPExsVywNykWHf6Eb4 Ig7XT2S2+b5nM5MDocfjDFZYAxijWzLyk/IoE1ox3Z6YxFuw2qvi0+AlbA+NO1S5GTg4hgQqJ neePsYPYEgK8EkeWzWCFsAMkWr49YOxi5AKqaWCU6L9yFKyITUBd4vHXHiYQW0RASeLeqslMI EXMAvsZJX69fMwCkhAWCJE4Me0+M4jNIqAq8XMGRAOvgLvEtWVToTbISZw8NhnM5hTwkLiz9z g7xEXuEn0NTYwTGHkXMDKsYtQoTi0qSy3SNTTXSyrKTM8oyU3MzNE1NDDTy00tLk5MT81JTCr WS87P3cQIDAgGINjBeHtjwCFGSQ4mJVHemZv4IoT4kvJTKjMSizPii0pzUosPMcpwcChJ8K4/ DJQTLEpNT61Iy8wBhiZMWoKDR0mE9wlImre4IDG3ODMdInWKUZdjy4Iba5mEWPLy81KlxHkXg RQJgBRllObBjYDFySVGWSlhXkago4R4ClKLcjNLUOVfMYpzMCoJ874AmcKTmVcCt+kV0BFMQE cIxvOAHFGSiJCSamD0O3mq4OXdSXPfpyVeyEg0Ekn7mpMqlnSYbc/57Z+uctz/brMyNGV/zZc 9xq1sNrdPqgRuklV9kVKye16WfohdwbRF9i9vnZ/n/v3ZK4YvRdEXli1OyHAu8rI7cjfg8bve 6YYXszOSj0m2aBick/ENe/C5ePfbxe/urhbTVpNmyg/zNPbkOJ+uxFKckWioxVxUnAgA4w0Qg Y4CAAA= X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1477362814!54875270!8 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.13; banners=-,-,- X-VirusChecked: Checked Received: (qmail 50146 invoked from network); 25 Oct 2016 02:33:58 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-14.tower-27.messagelabs.com with DHE-RSA-CAMELLIA256-SHA encrypted SMTP; 25 Oct 2016 02:33:58 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 24 Oct 2016 19:33:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,544,1473145200"; d="scan'208"; a="1049570175" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.60]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2016 19:33:56 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Tue, 25 Oct 2016 11:40:55 +0800 Message-Id: <1477366863-5246-8-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> References: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> Cc: wei.liu2@citrix.com, he.chen@linux.intel.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, Yi Sun , jbeulich@suse.com, chao.p.peng@linux.intel.com Subject: [Xen-devel] [PATCH v3 07/15] x86: refactor psr: Implement feature operations structure. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP To handle all features in a universal way, we need abstract the common operations of all features and register different callback functions for differnet features. The feature specific behaviors should be encapsulated into these callback functions. This patch defines 'struct feat_ops' to maintain features' callback functions. Also implement the L3 CAT/CDP init callback function to show how this mechanism work. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 123 ++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 84 insertions(+), 39 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 38a64f0..750278c 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -32,6 +32,21 @@ enum psr_feat_type { PSR_SOCKET_L3_CDP, }; +struct feat_node; +struct psr_cat_socket_info; + +/* Every feature enabled MUST implement such ops and callback functions. */ +struct feat_ops { + /* + * init_feature is used in cpu initialization process to do feature + * specific initialization works. + */ + void (*init_feature)(unsigned int eax, unsigned int ebx, + unsigned int ecx, unsigned int edx, + struct feat_node *feat, + struct psr_cat_socket_info *info); +}; + /* CAT/CDP HW info data structure. */ struct psr_cat_hw_info { unsigned int cbm_len; @@ -41,6 +56,8 @@ struct psr_cat_hw_info { struct feat_node { /* Which feature it is. */ enum psr_feat_type feature; + /* Feature operation callback functions. */ + struct feat_ops ops; /* Feature HW info. */ struct psr_cat_hw_info info; /* @@ -133,6 +150,69 @@ static void free_feature(struct psr_cat_socket_info *info) } } +/* L3 CAT/CDP callback functions implementation. */ +static void l3_cat_init_feature(unsigned int eax, unsigned int ebx, + unsigned int ecx, unsigned int edx, + struct feat_node *feat, + struct psr_cat_socket_info *info) +{ + struct psr_cat_hw_info l3_cat; + unsigned int socket; + uint64_t val; + + /* No valid value so do not enable feature. */ + if ( !eax || !edx ) + return; + + l3_cat.cbm_len = (eax & 0x1f) + 1; + l3_cat.cos_max = min(opt_cos_max, edx & 0xffff); + + /* cos=0 is reserved as default cbm(all ones). */ + feat->cos_reg_val[0] = (1ull << l3_cat.cbm_len) - 1; + + if ( (ecx & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) && + !test_bit(PSR_SOCKET_L3_CDP, &info->feat_mask) ) + { + /* CODE */ + get_cdp_code(feat, 0) = + (1ull << l3_cat.cbm_len) - 1; + /* DATA */ + get_cdp_data(feat, 0) = + (1ull << l3_cat.cbm_len) - 1; + + /* We only write mask1 since mask0 is always all ones by default. */ + wrmsrl(MSR_IA32_PSR_L3_MASK(1), + (1ull << l3_cat.cbm_len) - 1); + rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val); + wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT)); + + /* Cut half of cos_max when CDP is enabled. */ + l3_cat.cos_max >>= 1; + + feat->feature = PSR_SOCKET_L3_CDP; + __set_bit(PSR_SOCKET_L3_CDP, &info->feat_mask); + } else { + feat->feature = PSR_SOCKET_L3_CAT; + __set_bit(PSR_SOCKET_L3_CAT, &info->feat_mask); + } + + feat->info = l3_cat; + + info->nr_feat++; + + /* Add this feature into list. */ + list_add_tail(&feat->list, &info->feat_list); + + socket = cpu_to_socket(smp_processor_id()); + printk(XENLOG_INFO "L3 CAT: enabled on socket %u, cos_max:%u, cbm_len:%u, CDP:%s\n", + socket, feat->info.cos_max, feat->info.cbm_len, + test_bit(PSR_SOCKET_L3_CDP, &info->feat_mask) ? "on" : "off"); +} + +struct feat_ops l3_cat_ops = { + .init_feature = l3_cat_init_feature, +}; + static unsigned int get_socket_cpu(unsigned int socket) { if ( likely(socket < nr_sockets) ) @@ -683,7 +763,6 @@ static void cat_cpu_init(void) struct psr_cat_socket_info *info; unsigned int socket; unsigned int cpu = smp_processor_id(); - uint64_t val; const struct cpuinfo_x86 *c = cpu_data + cpu; struct feat_node *feat_tmp; @@ -695,6 +774,8 @@ static void cat_cpu_init(void) if ( info->feat_mask ) return; + spin_lock_init(&info->ref_lock); + cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx); if ( ebx & PSR_RESOURCE_TYPE_L3 ) { @@ -702,44 +783,8 @@ static void cat_cpu_init(void) feat_l3 = NULL; cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &ecx, &edx); - feat_tmp->info.cbm_len = (eax & 0x1f) + 1; - feat_tmp->info.cos_max = min(opt_cos_max, edx & 0xffff); - - /* cos=0 is reserved as default cbm(all ones). */ - feat_tmp->cos_reg_val[0] = (1ull << feat_tmp->info.cbm_len) - 1; - - spin_lock_init(&info->ref_lock); - - if ( (ecx & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) && - !test_bit(PSR_SOCKET_L3_CDP, &info->feat_mask) ) - { - /* CODE */ - get_cdp_code(feat_tmp, 0) = (1ull << feat_tmp->info.cbm_len) - 1; - /* DATA */ - get_cdp_data(feat_tmp, 0) = (1ull << feat_tmp->info.cbm_len) - 1; - - /* We only write mask1 since mask0 is always all ones by default. */ - wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << feat_tmp->info.cbm_len) - 1); - - rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val); - wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT)); - - /* Cut half of cos_max when CDP is enabled. */ - feat_tmp->info.cos_max >>= 1; - - __set_bit(PSR_SOCKET_L3_CDP, &info->feat_mask); - } else { - feat_tmp->feature = PSR_SOCKET_L3_CAT; - __set_bit(PSR_SOCKET_L3_CAT, &info->feat_mask); - } - - info->nr_feat++; - /* Add this feature into list. */ - list_add_tail(&feat_tmp->list, &info->feat_list); - - printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u, CDP:%s\n", - socket, feat_tmp->info.cos_max, feat_tmp->info.cbm_len, - cdp_is_enabled(socket) ? "on" : "off"); + feat_tmp->ops = l3_cat_ops; + feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info); } }