From patchwork Fri Nov 18 01:57:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wu, Feng" X-Patchwork-Id: 9435673 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EE4E360238 for ; Fri, 18 Nov 2016 02:32:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E25C42972B for ; Fri, 18 Nov 2016 02:32:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D6E6F29733; Fri, 18 Nov 2016 02:32:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 457D42972B for ; Fri, 18 Nov 2016 02:32:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1c7Ywg-00046X-LH; Fri, 18 Nov 2016 02:30:30 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1c7Ywf-00045k-0J for xen-devel@lists.xen.org; Fri, 18 Nov 2016 02:30:29 +0000 Received: from [85.158.137.68] by server-8.bemta-3.messagelabs.com id AA/0A-26755-4C76E285; Fri, 18 Nov 2016 02:30:28 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsVywNykWPdwul6 Ewa0V2hZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8afA1dZCpbqVDSvL25gPCDfxcjJISRQKdHS 0M8MYksI8EocWTaDFcIOkDj0ZzljFyMXUE0fo8SUG2+ZQBJsAooSBy8eAisSEZCWuPb5MlgRs 8ACRonGi0fBJgkDdR+c+A7MZhFQlXh0awkjiM0r4Cjx/+gKJogNchIbdv8Hi3MKOEkcX32bBe IiR4n9Uz+wTGDkXcDIsIpRozi1qCy1SNfIWC+pKDM9oyQ3MTNH19DAWC83tbg4MT01JzGpWC8 5P3cTIzAc6hkYGHcw9u31O8QoycGkJMrbHq0XIcSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mCtz8N KCdYlJqeWpGWmQMMTJi0BAePkgjvjVSgNG9xQWJucWY6ROoUo6KUOG8PSJ8ASCKjNA+uDRYNl xhlpYR5GRkYGIR4ClKLcjNLUOVfMYpzMCoJ824BmcKTmVcCN/0V0GImoMV7BHRAFpckIqSkGh jFLtXtkb0o6FJ7RNn3lbPeMa4HbtfPbpW7wBenLudan5mydNcTy1lKP9ZwiEZXMEzY/5pz/t4 PSTxvTSMkMrYXXDnU/+JBRMv9S/Lf0/pbLPczfCxwS6zcsTLptrnhrDcSN8pv/46fFin4hyNa uCTveLVsXVb32vOisuyerXmiGWcmxyxJ4FZiKc5INNRiLipOBADrYP6IgQIAAA== X-Env-Sender: feng.wu@intel.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1479436223!71575017!2 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 50057 invoked from network); 18 Nov 2016 02:30:26 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-3.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 18 Nov 2016 02:30:26 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 17 Nov 2016 18:30:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,655,1473145200"; d="scan'208"; a="1070084869" Received: from unknown (HELO feng-bdw-de-pi.bj.intel.com) ([10.238.154.55]) by fmsmga001.fm.intel.com with ESMTP; 17 Nov 2016 18:30:24 -0800 From: Feng Wu To: xen-devel@lists.xen.org Date: Fri, 18 Nov 2016 09:57:22 +0800 Message-Id: <1479434244-10223-6-git-send-email-feng.wu@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1479434244-10223-1-git-send-email-feng.wu@intel.com> References: <1479434244-10223-1-git-send-email-feng.wu@intel.com> Cc: kevin.tian@intel.com, Feng Wu , george.dunlap@eu.citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, jbeulich@suse.com Subject: [Xen-devel] [PATCH v8 5/7] VT-d: No need to set irq affinity for posted format IRTE X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP We don't set the affinity for posted format IRTE, since the destination of these interrupts is vCPU and the vCPU affinity is set during vCPU scheduling. Signed-off-by: Feng Wu --- v8: - Changes based on [6/7] v7: - Compare all the field in IRTE to justify whether we can suppress the update v6: - Make pi_can_suppress_irte_update() a check-only function - Introduce another function pi_get_new_irte() to update the 'new_ire' if needed v5: - Only suppress affinity related IRTE updates for PI v4: - Keep the construction of new_ire and only modify the hardware IRTE when it is not in posted mode. xen/drivers/passthrough/vtd/intremap.c | 87 ++++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index fd2a49a..0cb8c37 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -600,27 +600,41 @@ static int msi_msg_to_remap_entry( if ( !pi_desc ) { - /* Set interrupt remapping table entry */ - new_ire.remap.fpd = 0; - new_ire.remap.dm = (msg->address_lo >> MSI_ADDR_DESTMODE_SHIFT) & 0x1; - new_ire.remap.tm = (msg->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; - new_ire.remap.dlm = (msg->data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x1; - /* Hardware require RH = 1 for LPR delivery mode */ - new_ire.remap.rh = (new_ire.remap.dlm == dest_LowestPrio); - new_ire.remap.avail = 0; - new_ire.remap.res_1 = 0; - new_ire.remap.vector = (msg->data >> MSI_DATA_VECTOR_SHIFT) & - MSI_DATA_VECTOR_MASK; - new_ire.remap.res_2 = 0; - if ( x2apic_enabled ) - new_ire.remap.dst = msg->dest32; - else - new_ire.remap.dst = ((msg->address_lo >> MSI_ADDR_DEST_ID_SHIFT) - & 0xff) << 8; + /* + * We are here because we are trying to update the IRTE to remapped mode, + * we only need to update the remapped specific fields for the following + * two cases: + * 1. When we create a new IRTE. A new IRTE is created when we create a + * new irq, so a new IRTE is always initialized with remapped format. + * 2. When the old IRTE is present and in remapped mode. Since if the old + * IRTE is in posted mode, we cannot update it to remapped mode and + * this is what we need to suppress. So we don't update the remapped + * specific fields here, we only update the commom field. + */ + if ( !iremap_entry->remap.p || !iremap_entry->remap.im ) + { + /* Set interrupt remapping table entry */ + new_ire.remap.fpd = 0; + new_ire.remap.dm = (msg->address_lo >> MSI_ADDR_DESTMODE_SHIFT) & 0x1; + new_ire.remap.tm = (msg->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; + new_ire.remap.dlm = (msg->data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x1; + /* Hardware require RH = 1 for LPR delivery mode */ + new_ire.remap.rh = (new_ire.remap.dlm == dest_LowestPrio); + new_ire.remap.avail = 0; + new_ire.remap.res_1 = 0; + new_ire.remap.vector = (msg->data >> MSI_DATA_VECTOR_SHIFT) & + MSI_DATA_VECTOR_MASK; + new_ire.remap.res_2 = 0; + if ( x2apic_enabled ) + new_ire.remap.dst = msg->dest32; + else + new_ire.remap.dst = ((msg->address_lo >> MSI_ADDR_DEST_ID_SHIFT) + & 0xff) << 8; - new_ire.remap.res_3 = 0; - new_ire.remap.res_4 = 0; - new_ire.remap.p = 1; /* finally, set present bit */ + new_ire.remap.res_3 = 0; + new_ire.remap.res_4 = 0; + new_ire.remap.p = 1; /* finally, set present bit */ + } } else { @@ -657,25 +671,28 @@ static int msi_msg_to_remap_entry( remap_rte->address_hi = 0; remap_rte->data = index - i; - if ( !pi_desc ) - memcpy(iremap_entry, &new_ire, sizeof(struct iremap_entry)); - else + if ( iremap_entry->val != new_ire.val ) { - __uint128_t ret; + if ( !pi_desc ) + memcpy(iremap_entry, &new_ire, sizeof(struct iremap_entry)); + else + { + __uint128_t ret; - old_ire = *iremap_entry; - ret = cmpxchg16b(iremap_entry, &old_ire, &new_ire); + old_ire = *iremap_entry; + ret = cmpxchg16b(iremap_entry, &old_ire, &new_ire); - /* - * In the above, we use cmpxchg16 to atomically update the 128-bit IRTE, - * and the hardware cannot update the IRTE behind us, so the return value - * of cmpxchg16 should be the same as old_ire. This ASSERT validate it. - */ - ASSERT(ret == old_ire.val); - } + /* + * In the above, we use cmpxchg16 to atomically update the 128-bit IRTE, + * and the hardware cannot update the IRTE behind us, so the return value + * of cmpxchg16 should be the same as old_ire. This ASSERT validate it. + */ + ASSERT(ret == old_ire.val); + } - iommu_flush_cache_entry(iremap_entry, sizeof(struct iremap_entry)); - iommu_flush_iec_index(iommu, 0, index); + iommu_flush_cache_entry(iremap_entry, sizeof(struct iremap_entry)); + iommu_flush_iec_index(iommu, 0, index); + } unmap_vtd_domain_page(iremap_entries); spin_unlock_irqrestore(&ir_ctrl->iremap_lock, flags);