@@ -1403,6 +1403,12 @@ long arch_do_domctl(
PSR_CBM_TYPE_L3_DATA);
break;
+ case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
+ ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+ domctl->u.psr_cat_op.data,
+ PSR_CBM_TYPE_L2);
+ break;
+
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_cat_op.target,
&domctl->u.psr_cat_op.data,
@@ -796,17 +796,127 @@ static bool l2_cat_get_val(const struct feat_node *feat, unsigned int cos,
if ( cos > feat->info.l2_cat_info.cos_max )
cos = 0;
- /* L2 CAT */
*val = feat->cos_reg_val[cos];
return true;
}
+static unsigned int l2_cat_get_cos_num(const struct feat_node *feat)
+{
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
+static int l2_cat_get_old_val(uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int old_cos)
+{
+ if ( old_cos > feat->info.l2_cat_info.cos_max )
+ /* Use default value. */
+ old_cos = 0;
+
+ val[0] = feat->cos_reg_val[old_cos];
+
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
+static int l2_cat_set_new_val(uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int old_cos,
+ enum cbm_type type,
+ uint64_t m)
+{
+ if ( type != PSR_CBM_TYPE_L2 )
+ return 1;
+
+ if ( !psr_check_cbm(feat->info.l2_cat_info.cbm_len, m) )
+ return -EINVAL;
+
+ val[0] = m;
+
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
+static unsigned int l2_cat_get_cos_max_from_type(const struct feat_node *feat,
+ enum cbm_type type)
+{
+ if ( type != PSR_CBM_TYPE_L2 )
+ return 0;
+
+ return feat->info.l2_cat_info.cos_max;
+}
+
+static int l2_cat_compare_val(const uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int cos, bool *found)
+{
+ uint64_t l2_def_cbm;
+
+ l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+ if ( cos > feat->info.l2_cat_info.cos_max )
+ {
+ if ( val[0] != l2_def_cbm )
+ {
+ *found = false;
+ return -ENOENT;
+ }
+ *found = true;
+ }
+ else
+ *found = (val[0] == feat->cos_reg_val[cos]);
+
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
+static unsigned int l2_cat_exceeds_cos_max(const uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int cos)
+{
+ uint64_t l2_def_cbm;
+
+ l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+ if ( cos > feat->info.l2_cat_info.cos_max &&
+ val[0] != l2_def_cbm )
+ /*
+ * Exceed cos_max and value to set is not default,
+ * return error.
+ */
+ return 0;
+
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
+static int l2_cat_write_msr(unsigned int cos, const uint64_t val[],
+ struct feat_node *feat)
+{
+ if ( cos > feat->info.l2_cat_info.cos_max )
+ return 1;
+
+ feat->cos_reg_val[cos] = val[0];
+ wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val[0]);
+
+ /* L2 CAT uses one COS. */
+ return 1;
+}
+
struct feat_ops l2_cat_ops = {
.init_feature = l2_cat_init_feature,
.get_max_cos_max = l2_cat_get_max_cos_max,
.get_feat_info = l2_cat_get_feat_info,
.get_val = l2_cat_get_val,
+ .get_cos_num = l2_cat_get_cos_num,
+ .get_old_val = l2_cat_get_old_val,
+ .set_new_val = l2_cat_set_new_val,
+ .get_cos_max_from_type = l2_cat_get_cos_max_from_type,
+ .compare_val = l2_cat_compare_val,
+ .exceeds_cos_max = l2_cat_exceeds_cos_max,
+ .write_msr = l2_cat_write_msr,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -1317,10 +1427,30 @@ int psr_set_val(struct domain *d, unsigned int socket,
uint64_t *val_array;
struct psr_socket_info *info = get_socket_info(socket);
uint32_t array_len;
+ uint32_t flag;
if ( IS_ERR(info) )
return PTR_ERR(info);
+ /* Judge if feature is enabled. */
+ switch ( type ) {
+ case PSR_CBM_TYPE_L3:
+ flag = PSR_SOCKET_L3_CAT;
+ break;
+ case PSR_CBM_TYPE_L3_DATA:
+ case PSR_CBM_TYPE_L3_CODE:
+ flag = PSR_SOCKET_L3_CDP;
+ break;
+ case PSR_CBM_TYPE_L2:
+ flag = PSR_SOCKET_L2_CAT;
+ break;
+ default:
+ flag = 0xFFFF;
+ break;
+ }
+ if ( !test_bit(flag, &info->feat_mask) )
+ return -ENODEV;
+
/*
* Step 0:
* old_cos means the COS ID current domain is using. By default, it is 0.
@@ -343,6 +343,7 @@
#define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n))
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
@@ -1137,6 +1137,7 @@ struct xen_domctl_psr_cat_op {
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA 3
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE 4
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
This patch implements L2 CAT set value related callback functions and domctl interface. Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> --- xen/arch/x86/domctl.c | 6 ++ xen/arch/x86/psr.c | 132 +++++++++++++++++++++++++++++++++++++++- xen/include/asm-x86/msr-index.h | 1 + xen/include/public/domctl.h | 1 + 4 files changed, 139 insertions(+), 1 deletion(-)