diff mbox

[v3,3/3] xen/arm: acpi: Relax hw domain mapping attributes to p2m_mmio_direct_c

Message ID 1485901080-8802-4-git-send-email-edgar.iglesias@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Edgar E. Iglesias Jan. 31, 2017, 10:18 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Since the hardware domain is a trusted domain, we extend the
trust to include making final decisions on what attributes to
use when mapping memory regions.

For ACPI configured hardware domains, this patch relaxes the hardware
domains mapping attributes to p2m_mmio_direct_c. This will allow the
hardware domain to control the attributes via its S1 mappings.

Acked-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 xen/arch/arm/p2m.c          | 2 +-
 xen/include/public/memory.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
diff mbox

Patch

diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index 09ceb37..cb5a45d 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -1185,7 +1185,7 @@  int map_dev_mmio_region(struct domain *d,
     if ( !(nr && iomem_access_permitted(d, mfn_x(mfn), mfn_x(mfn) + nr - 1)) )
         return 0;
 
-    res = map_mmio_regions(d, gfn, nr, mfn);
+    res = p2m_insert_mapping(d, gfn, nr, mfn, p2m_mmio_direct_c);
     if ( res < 0 )
     {
         printk(XENLOG_G_ERR "Unable to map MFNs [%#"PRI_mfn" - %#"PRI_mfn" in Dom%d\n",
diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h
index e633047..6eee0c8 100644
--- a/xen/include/public/memory.h
+++ b/xen/include/public/memory.h
@@ -222,9 +222,9 @@  DEFINE_XEN_GUEST_HANDLE(xen_machphys_mapping_t);
                                     * XENMEM_add_to_physmap_batch only. */
 #define XENMAPSPACE_dev_mmio     5 /* device mmio region
                                       ARM only; the region is mapped in
-                                      Stage-2 using the memory attribute
-                                      "Device-nGnRE" (previously named
-                                      "Device" on ARMv7) */
+                                      Stage-2 using the Normal Memory
+                                      Inner/Outer Write-Back Cacheable
+                                      memory attribute. */
 /* ` } */
 
 /*