From patchwork Thu Mar 16 11:08:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9627865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0644E6048C for ; Thu, 16 Mar 2017 11:16:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2A4B28573 for ; Thu, 16 Mar 2017 11:16:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E754C2857D; Thu, 16 Mar 2017 11:16:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3A952285B5 for ; Thu, 16 Mar 2017 11:16:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTMU-0004px-An; Thu, 16 Mar 2017 11:14:30 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTMT-0004or-J5 for xen-devel@lists.xenproject.org; Thu, 16 Mar 2017 11:14:29 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id BC/68-12861-4937AC85; Thu, 16 Mar 2017 11:14:28 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRWlGSWpSXmKPExsVywNwkVndK8ak Ig6YZ0hbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8apXVsYC+4qVaw6eJ+tgfG8VBcjFweLwC0m iadLm1m7GDk5hASmMUr8nhABYksI8EocWTaDFcL2l3jTuJEdpEFIoIFRonnWXLAEm4C6xOOvP UwgtoiAksS9VZOZQIqYBXYySaw7/Z25i5GDQ1jAQ+L8d3GQGhYBVYnpU64wg9i8QOGm1feYIB bISZw8NhlsJidQ/GN7O9RB7hLvNvxln8DIt4CRYRWjRnFqUVlqka6hiV5SUWZ6RkluYmaOrqG BsV5uanFxYnpqTmJSsV5yfu4mRmCgMADBDsYV2z0PMUpyMCmJ8pb/OBEhxJeUn1KZkVicEV9U mpNafIhRhoNDSYL3iNLJCCHBotT01Iq0zBxgyMKkJTh4lER4c0HSvMUFibnFmekQqVOMilLiv BdAEgIgiYzSPLg2WJxcYpSVEuZlBDpEiKcgtSg3swRV/hWjOAejkjDvZpApPJl5JXDTXwEtZg Ja/PbDCZDFJYkIKakGRtb+bVOiOtbeubB3w4Yos9Sya6c4IiKPRs5e5h0XeensQetX8Wk/Zlu Ue8Xf/H3uxq8XnlOy35u7LznLYViodXpaivCErJlRN/KqhJ6/bWuZ8Tv9DMf5x+a1Kdslp3BO OZIoZrdNZ+Wu7P9NG6RfMN4/vtB9m/S7/gzf8tW1W3lcpGZeNlh65o4SS3FGoqEWc1FxIgANW 1fOjgIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-2.tower-31.messagelabs.com!1489662818!78881615!17 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12965 invoked from network); 16 Mar 2017 11:14:27 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-2.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 16 Mar 2017 11:14:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489662867; x=1521198867; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=AjbQvWWg9DDA26qOM0sbC99wHxSLSS4mg7CrXRGTfEc=; b=SbYeDa9Ku0ABV2E0MMNcLuLv1wh3e8NQRvr7xLC55XigSNWOtsqMRBeo qCP1ncf0yTjvdjRmDbNoeLt1CQBKDw==; Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Mar 2017 04:14:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,172,1486454400"; d="scan'208";a="944976702" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.63]) by orsmga003.jf.intel.com with ESMTP; 16 Mar 2017 04:14:23 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Thu, 16 Mar 2017 19:08:08 +0800 Message-Id: <1489662495-5375-19-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489662495-5375-1-git-send-email-yi.y.sun@linux.intel.com> References: <1489662495-5375-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v9 18/25] x86: L2 CAT: implement CPU init and free flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init and free flow for L2 CAT including L2 CAT initialization callback function. Signed-off-by: Yi Sun --- v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 27 ++++++++++++++++++++++++++- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 1 + 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 7ede8a1..576914d 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -213,6 +213,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3_cat; static struct feat_node *feat_l3_cdp; +static struct feat_node *feat_l2_cat; /* Common functions */ #define cat_default_val(len) \ @@ -371,7 +372,11 @@ static void cat_init_feature(struct cpuid_leaf regs, */ for ( i = 1; i <= cat.cos_max; i++ ) { - rdmsrl(MSR_IA32_PSR_L3_MASK(i), val); + if ( type == PSR_SOCKET_L3_CAT ) + rdmsrl(MSR_IA32_PSR_L3_MASK(i), val); + else + rdmsrl(MSR_IA32_PSR_L2_MASK(i), val); + feat->cos_reg_val[i] = (uint32_t)val; } } @@ -627,6 +632,11 @@ struct feat_ops l3_cdp_ops = { .write_msr = l3_cdp_write_msr, }; +/* L2 CAT ops */ +struct feat_ops l2_cat_ops = { + .get_cos_max = cat_get_cos_max, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1427,6 +1437,10 @@ static int psr_cpu_prepare(void) (feat_l3_cdp = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2_cat == NULL && + (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1479,6 +1493,17 @@ static void psr_cpu_init(void) } } + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); + + feat = feat_l2_cat; + feat_l2_cat = NULL; + feat->ops = l2_cat_ops; + cat_init_feature(regs, feat, info, PSR_SOCKET_L2_CAT); + } + assoc_init: psr_assoc_init(); } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 771e750..6c49c6d 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -345,6 +345,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index d2262d9..4e392c8 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1