From patchwork Thu Mar 16 11:07:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9627903 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8E9916048C for ; Thu, 16 Mar 2017 11:16:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8441E2857D for ; Thu, 16 Mar 2017 11:16:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78D25285B5; Thu, 16 Mar 2017 11:16:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C9BD2857D for ; Thu, 16 Mar 2017 11:16:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTLq-0004As-Kp; Thu, 16 Mar 2017 11:13:50 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTLp-0004Af-Cg for xen-devel@lists.xenproject.org; Thu, 16 Mar 2017 11:13:49 +0000 Received: from [85.158.137.68] by server-17.bemta-3.messagelabs.com id 7A/D2-04270-C637AC85; Thu, 16 Mar 2017 11:13:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeJIrShJLcpLzFFi42I5YG4Sq5tdfCr C4O8FVYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNWPzwlfMBVtSKrr/3mRtYNzr3cXIycEicItJ YsoD9S5GLg4hgWmMEt93HmcHSUgI8EocWTaDFcL2l9j87DojRFEDo8SBg4+YQRJsAuoSj7/2M IHYIgJKEvdWTWYCKWIW2Mkkse70d6AiDg5hgTCJb+dsIbapSsxc/I4NxOYVcJfo+XyIGWKBnM TJY5PBlnEKeEh8bG8Hs4WAat5t+Ms+gZFvASPDKkaN4tSistQiXUMTvaSizPSMktzEzBxdQwN jvdzU4uLE9NScxKRiveT83E2MwEBhAIIdjCu2ex5ilORgUhLlLf9xIkKILyk/pTIjsTgjvqg0 J7X4EKMMB4eSBO8RpZMRQoJFqempFWmZOcCQhUlLcPAoifDmgqR5iwsSc4sz0yFSpxh1OebM3 v2GSYglLz8vVUqc9wJIkQBIUUZpHtwIWPxcYpSVEuZlBDpKiKcgtSg3swRV/hWjOAejkjDvZp ApPJl5JXCbXgEdwQR0xNsPJ0COKElESEk1MFp7mIWq5hxZ4HQ2rP9LRuCF9AdyOZkGnatWRjp vVCj38xPfIyb5TN84d37A4SzGFlUWgzl5bVYZd579WPHh2ex7+mcc7Bft/nj4wD3BD0EW7+su CXybtuGV9JUExsLDPyr5Km5vs3uxiPWJREtlbMAMX/U/7oVPDsasrxObf8+lP7FeRuDXIiWW4 oxEQy3mouJEAFGX3XGaAgAA X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-2.tower-31.messagelabs.com!1489662818!78881615!4 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5782 invoked from network); 16 Mar 2017 11:13:46 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-2.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 16 Mar 2017 11:13:46 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489662826; x=1521198826; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=W92wrD8n1e7kAW0aKO0AYiLRfy3TxEMZwPk8Spwl+1E=; b=CkSnNXDiHnKc7Fuj3UysuHpsSle4QNMmKtkqbEIObAw7Jrmydx2YEZ11 ZYUg7ClwkiEwMVtGH/q4HTC4agEFNQ==; Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Mar 2017 04:13:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,172,1486454400"; d="scan'208";a="944976366" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.63]) by orsmga003.jf.intel.com with ESMTP; 16 Mar 2017 04:13:43 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Thu, 16 Mar 2017 19:07:55 +0800 Message-Id: <1489662495-5375-6-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489662495-5375-1-git-send-email-yi.y.sun@linux.intel.com> References: <1489662495-5375-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v9 05/25] x86: refactor psr: L3 CAT: implement CPU init and free flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init and free flow including L3 CAT initialization and feature array free. It includes below flows: 1. presmp init: - parse command line parameter. - allocate socket info for every socket. - allocate feature resource. - initialize socket info, get feature info and add feature into feature array per cpuid result. - free resources allocated if error happens. - register cpu notifier to handle cpu events. 2. cpu notifier: - handle cpu online events, if initialization work has been done before, do nothing. - handle cpu offline events, if it is the last cpu offline, free feature resources. Signed-off-by: Yi Sun --- v9: - add commit message to explain the flows. - handle cpu offline and online again case to read MSRs registers values back and save them into cos array to make user can get real data. - create a new patch about moving 'cpuid_count_leaf'. (suggested by Wei Liu) - modify comment to explain why not free some resource in 'free_feature'. (suggested by Wei Liu) - implement 'psr_alloc_feat_enabled' to check if allocation feature is enabled in cmdline and some initialization work done. (suggested by Wei Liu) - implement 'cat_default_val' to set default value for CAT features. (suggested by Wei Liu) - replace feature list handling to feature array handling. (suggested by Roger Pau) - implement a common 'cat_init_feature' to replace L3 CAT/L2 CAT specific init functions. (suggested by Roger Pau) - modify comments for global feature node. (suggested by Jan Beulich) - remove unnecessary comments. (suggested by Jan Beulich) - remove unnecessary 'else'. (suggested by Jan Beulich) - remove 'nr_feat'. (suggested by Jan Beulich) - modify patch title to indicate 'L3 CAT'. (suggested by Jan Beulich) - check global flag with boot cpu operations. (suggested by Jan Beulich) - remove 'cpu_init_work' and move codes into 'psr_cpu_init'. (suggested by Jan Beulich) - remove 'cpu_fini_work' and move codes into 'psr_cpu_fini'. (suggested by Jan Beulich) - assign value for 'cos_num'. (suggested by Jan Beulich) - change about 'uint64_t' to 'uint32_t'. (suggested by Jan Beulich) v8: - fix format issue. (suggested by Konrad Rzeszutek Wilk) - add comments to explain why we care about cpumask_empty when the last cpu on socket is offline. (suggested by Konrad Rzeszutek Wilk) v7: - initialize structure objects for avoiding surprise. (suggested by Konrad Rzeszutek Wilk) - fix typo. (suggested by Konrad Rzeszutek Wilk) - fix a logical mistake when handling the last cpu offline event. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf' introduced in Andrew's patch. (suggested by Konrad Rzeszutek Wilk) - add comments about cpu_add_remove_lock. (suggested by Konrad Rzeszutek Wilk) - change 'clear_bit' to '__clear_bit'. (suggested by Konrad Rzeszutek Wilk) - add 'ASSERT' check when setting 'feat_mask'. (suggested by Konrad Rzeszutek Wilk) - adjust 'printk' position to avoid odd spacing. (suggested by Konrad Rzeszutek Wilk) - add comment to explain usage of 'feat_l3_cat'. (suggested by Konrad Rzeszutek Wilk) - fix wording. (suggested by Konrad Rzeszutek Wilk) - move 'cpuid_count_leaf' helper function to 'asm-x86/processor.h'. It cannot be moved to 'cpuid.h' which causes compilation error because of header file loop reference. (suggested by Andrew Cooper) v5: - add comment to explain the reason to define 'feat_l3_cat'. (suggested by Jan Beulich) - use 'list_for_each_entry_safe'. (suggested by Jan Beulich) - remove codes to free 'feat_l3_cat' in 'free_feature' to avoid the need for an allocation the next time a CPU comes online. (suggested by Jan Beulich) - define 'struct cpuid_leaf_regs' to encapsulate eax~edx. (suggested by Jan Beulich) - print feature info on a socket only when 'opt_cpu_info' is true. (suggested by Jan Beulich) - declare global variable 'l3_cat_ops' to 'static const'. (suggested by Jan Beulich) - use 'current_cpu_data'. (suggested by Jan Beulich) - rename 'feat_tmp' to 'feat'. (suggested by Jan Beulich) - clear PQE feature bit when the maximum CPUID level is too low. (suggested by Jan Beulich) - directly call 'l3_cat_init_feature'. No need to make it a callback function. (suggested by Jan Beulich) - remove local variable 'info'. (suggested by Jan Beulich) - move 'INIT_LIST_HEAD' into 'cpu_init_work' to be together with spin_lock_init(). (suggested by Jan Beulich) - remove 'cpu_prepare_work' and move its content into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of removing all CAT/CDP old codes to make implementation be more easily understood. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 202 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 197 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 822f1c0..66a9ce8 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -18,6 +18,7 @@ #include #include #include +#include /* * Terminology: @@ -34,6 +35,9 @@ #define PSR_CAT (1<<1) #define PSR_CDP (1<<2) +#define CAT_CBM_LEN_MASK 0x1f +#define CAT_COS_MAX_MASK 0xffff + /* * Per SDM chapter 'Cache Allocation Technology: Cache Mask Configuration', * the MSRs ranging from 0C90H through 0D0FH (inclusive), enables support for @@ -46,6 +50,9 @@ */ #define MAX_COS_REG_CNT 128 +/* CAT features use 1 COS register in one access. */ +#define CAT_COS_NUM 1 + enum psr_feat_type { PSR_SOCKET_L3_CAT = 0, PSR_SOCKET_L3_CDP, @@ -126,11 +133,110 @@ struct psr_assoc { struct psr_cmt *__read_mostly psr_cmt; +static struct psr_socket_info *__read_mostly socket_info; + static unsigned int opt_psr; static unsigned int __initdata opt_rmid_max = 255; +static unsigned int __read_mostly opt_cos_max = MAX_COS_REG_CNT; static uint64_t rmid_mask; static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); +/* + * Declare global feature node for every feature to facilitate the feature + * array creation. It is used to transiently store a spare node. + */ +static struct feat_node *feat_l3_cat; + +/* Common functions */ +#define cat_default_val(len) \ + ( (uint32_t)((1ul << len) - 1) ) + +/* + * Use this function to check if any allocation feature has been enabled + * in cmdline. + */ +static bool psr_alloc_feat_enabled(void) +{ + return ((!socket_info) ? false : true ); +} + +static void free_feature(struct psr_socket_info *info) +{ + unsigned int i; + + if ( !info ) + return; + + /* + * Free resources of features. The global feature object, e.g. feat_l3_cat, + * may not be freed here if it is not added into array. It is simply being + * kept until the next CPU online attempt. + */ + for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ ) + { + if ( !info->features[i] ) + continue; + + xfree(info->features[i]); + info->features[i] = NULL; + __clear_bit(i, &info->feat_mask); + } +} + +/* CAT common functions implementation. */ +static void cat_init_feature(struct cpuid_leaf regs, + struct feat_node *feat, + struct psr_socket_info *info, + enum psr_feat_type type) +{ + unsigned int socket, i; + struct psr_cat_hw_info cat = { }; + uint64_t val; + + /* No valid value so do not enable feature. */ + if ( !regs.a || !regs.d ) + return; + + cat.cbm_len = (regs.a & CAT_CBM_LEN_MASK) + 1; + cat.cos_max = min(opt_cos_max, regs.d & CAT_COS_MAX_MASK); + + /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ + feat->cos_reg_val[0] = cat_default_val(cat.cbm_len); + /* + * To handle cpu offline and then online case, we need read MSRs back to + * save values into cos_reg_val array. + */ + for ( i = 1; i <= cat.cos_max; i++ ) + { + rdmsrl(MSR_IA32_PSR_L3_MASK(i), val); + feat->cos_reg_val[i] = (uint32_t)val; + } + + feat->info.cat_info = cat; + feat->cos_num = CAT_COS_NUM; + + /* Add this feature into array. */ + info->features[type] = feat; + + ASSERT(!test_bit(type, &info->feat_mask)); + __set_bit(type, &info->feat_mask); + + socket = cpu_to_socket(smp_processor_id()); + if ( !opt_cpu_info ) + return; + + printk(XENLOG_INFO "%s CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n", + ((type == PSR_SOCKET_L3_CAT) ? "L3" : "L2"), + socket, feat->info.cat_info.cos_max, + feat->info.cat_info.cbm_len); + + return; +} + +/* L3 CAT ops */ +static const struct feat_ops l3_cat_ops = { +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -170,6 +276,9 @@ static void __init parse_psr_param(char *s) if ( val_str && !strcmp(s, "rmid_max") ) opt_rmid_max = simple_strtoul(val_str, NULL, 0); + if ( val_str && !strcmp(s, "cos_max") ) + opt_cos_max = simple_strtoul(val_str, NULL, 0); + s = ss + 1; } while ( ss ); } @@ -325,19 +434,98 @@ void psr_domain_free(struct domain *d) psr_free_rmid(d); } -static int psr_cpu_prepare(unsigned int cpu) +static void __init init_psr(void) { + if ( opt_cos_max < 1 ) + { + printk(XENLOG_INFO "CAT: disabled, cos_max is too small\n"); + return; + } + + socket_info = xzalloc_array(struct psr_socket_info, nr_sockets); + + if ( !socket_info ) + { + printk(XENLOG_INFO "Failed to alloc socket_info!\n"); + return; + } +} + +static void __init psr_free(void) +{ + xfree(socket_info); + socket_info = NULL; +} + +static int psr_cpu_prepare(void) +{ + if ( !psr_alloc_feat_enabled() ) + return 0; + + /* Malloc memory for the global feature head here. */ + if ( feat_l3_cat == NULL && + (feat_l3_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } static void psr_cpu_init(void) { + struct psr_socket_info *info; + unsigned int socket, i; + unsigned int cpu = smp_processor_id(); + struct feat_node *feat; + struct cpuid_leaf regs; + + if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) ) + goto assoc_init; + + if ( boot_cpu_data.cpuid_level < PSR_CPUID_LEVEL_CAT ) + { + setup_clear_cpu_cap(X86_FEATURE_PQE); + goto assoc_init; + } + + socket = cpu_to_socket(cpu); + info = socket_info + socket; + if ( info->feat_mask ) + goto assoc_init; + + for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ ) + info->features[i] = NULL; + + spin_lock_init(&info->ref_lock); + + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L3 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s); + + feat = feat_l3_cat; + feat_l3_cat = NULL; + feat->ops = l3_cat_ops; + + cat_init_feature(regs, feat, info, PSR_SOCKET_L3_CAT); + } + +assoc_init: psr_assoc_init(); } static void psr_cpu_fini(unsigned int cpu) { - return; + unsigned int socket = cpu_to_socket(cpu); + + if ( !psr_alloc_feat_enabled() ) + return; + + /* + * We only free when we are the last CPU in the socket. The socket_cpumask + * is cleared prior to this notification code by remove_siblinginfo(). + */ + if ( socket_cpumask[socket] && cpumask_empty(socket_cpumask[socket]) ) + free_feature(socket_info + socket); } static int cpu_callback( @@ -349,7 +537,7 @@ static int cpu_callback( switch ( action ) { case CPU_UP_PREPARE: - rc = psr_cpu_prepare(cpu); + rc = psr_cpu_prepare(); break; case CPU_STARTING: psr_cpu_init(); @@ -378,10 +566,14 @@ static int __init psr_presmp_init(void) if ( (opt_psr & PSR_CMT) && opt_rmid_max ) init_psr_cmt(opt_rmid_max); - psr_cpu_prepare(0); + if ( opt_psr & PSR_CAT ) + init_psr(); + + if ( psr_cpu_prepare() ) + psr_free(); psr_cpu_init(); - if ( psr_cmt_enabled() ) + if ( psr_cmt_enabled() || psr_alloc_feat_enabled() ) register_cpu_notifier(&cpu_nfb); return 0;