From patchwork Fri Mar 17 11:27:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9630431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E30A960249 for ; Fri, 17 Mar 2017 11:37:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCC96284E9 for ; Fri, 17 Mar 2017 11:37:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1B3C2862B; Fri, 17 Mar 2017 11:37:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 66CB128616 for ; Fri, 17 Mar 2017 11:37:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coqAT-00043g-D6; Fri, 17 Mar 2017 11:35:37 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coqAR-00041o-Tl for xen-devel@lists.xen.org; Fri, 17 Mar 2017 11:35:36 +0000 Received: from [85.158.137.68] by server-5.bemta-3.messagelabs.com id 67/14-19998-70ACBC85; Fri, 17 Mar 2017 11:35:35 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRWlGSWpSXmKPExsXS1tYhost26nS Ewe9OfYslHxezODB6HN39mymAMYo1My8pvyKBNePj7N8sBfeUKm6tPcfYwDhVqouRi4NF4BaT xN+3m5lBHCGB6YwS05sOMnUxcnJICPBKHFk2gxXC9pM4cvQtO0RRP6NEx86bLCAJNgF1iROLJ zKC2CIC0hLXPl9mBCliFmhklGjY28gGkhAWsJP48WMt2CQWAVWJjSvngTXwCrhK3LvwDmgbB9 AGBYk5k2xAwpxA4bttD9hBbCEBF4l7XVdYJjDyLWBkWMWoXpxaVJZapGuol1SUmZ5RkpuYmaN raGCsl5taXJyYnpqTmFSsl5yfu4kRGCgMQLCDcflHp0OMkhxMSqK8J51ORgjxJeWnVGYkFmfE F5XmpBYfYpTh4FCS4OUJBMoJFqWmp1akZeYAQxYmLcHBoyTC+yEAKM1bXJCYW5yZDpE6xagoJ c77HqRPACSRUZoH1waLk0uMslLCvIxAhwjxFKQW5WaWoMq/YhTnYFQS5v0DMp4nM68EbvoroM VMQIvffjgBsrgkESEl1cDIM+3egTV8a7pOPzngE/uyJSomgu2Jmfen8kjxnfdnZ0rO0LnCdt9 s8cmiEoXaAwElgb0lHx4nvJze3Z0bdDVKp93x42WpvrtZr54yHjwfdL4yJ/n/QUkmIYnA6XOf Bt4K37Y5bymzk75I++fKE3uP3gk9Pf9tXsOErqM3Fta4L/u8Oy9Ff3GIEktxRqKhFnNRcSIA1 U1kE44CAAA= X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-7.tower-31.messagelabs.com!1489750532!83225957!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23656 invoked from network); 17 Mar 2017 11:35:34 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-7.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Mar 2017 11:35:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489750534; x=1521286534; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cyfgZRQkfc0HTpFcnTRhIRTC9HJrlLDSk+29c3K9rpw=; b=oxdPuR8D7wM+G4DVkaAnccJuKjkeKQU2c2+n29KFsarjHDrw4k2j+jQz nnsK7gUqSk1BupH9OCsm0M8NDcBSVg==; Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Mar 2017 04:35:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,176,1486454400"; d="scan'208";a="77573520" Received: from lantianyu-ws.sh.intel.com (HELO localhost) ([10.239.159.159]) by fmsmga005.fm.intel.com with ESMTP; 17 Mar 2017 04:35:23 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Fri, 17 Mar 2017 19:27:11 +0800 Message-Id: <1489750043-17260-12-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489750043-17260-1-git-send-email-tianyu.lan@intel.com> References: <1489750043-17260-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , andrew.cooper3@citrix.com, kevin.tian@intel.com, jbeulich@suse.com, chao.gao@intel.com Subject: [Xen-devel] [RFC PATCH 11/23] X86/vvtd: Add MMIO handler for VVTD X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao This patch is to add VVTD MMIO handler to deal with MMIO access. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/arch/x86/hvm/vvtd.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/xen/arch/x86/hvm/vvtd.c b/xen/arch/x86/hvm/vvtd.c index 13842b9..9473fe0 100644 --- a/xen/arch/x86/hvm/vvtd.c +++ b/xen/arch/x86/hvm/vvtd.c @@ -49,6 +49,38 @@ struct vvtd { struct page_info *regs_page; }; +#define __DEBUG_VVTD__ +#ifdef __DEBUG_VVTD__ +extern unsigned int vvtd_debug_level; +#define VVTD_DBG_INFO 1 +#define VVTD_DBG_TRANS (1<<1) +#define VVTD_DBG_RW (1<<2) +#define VVTD_DBG_FAULT (1<<3) +#define VVTD_DBG_EOI (1<<4) +#define VVTD_DEBUG(lvl, _f, _a...) do { \ + if ( vvtd_debug_level & lvl ) \ + printk("VVTD %s:" _f "\n", __func__, ## _a); \ +} while(0) +#else +#define VVTD_DEBUG(fmt...) do {} while(0) +#endif + +unsigned int vvtd_debug_level __read_mostly; +integer_param("vvtd_debug", vvtd_debug_level); + +struct vvtd *domain_vvtd(struct domain *d) +{ + struct viommu_info *info = &d->viommu; + + BUILD_BUG_ON(NR_VIOMMU_PER_DOMAIN != 1); + return (info && info->viommu[0]) ? info->viommu[0]->priv : NULL; +} + +static inline struct vvtd *vcpu_vvtd(struct vcpu *v) +{ + return domain_vvtd(v->domain); +} + static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg, uint32_t value) { @@ -75,6 +107,108 @@ static inline uint8_t vvtd_get_reg_byte(struct vvtd *vtd, uint32_t reg) vvtd_set_reg(vvtd, (reg) + 4, (uint32_t)((val) >> 32)); \ } while(0) +static int vvtd_range(struct vcpu *v, unsigned long addr) +{ + struct vvtd *vvtd = vcpu_vvtd(v); + + if ( vvtd ) + return (addr >= vvtd->base_addr) && + (addr < vvtd->base_addr + PAGE_SIZE); + return 0; +} + +static int vvtd_read(struct vcpu *v, unsigned long addr, + unsigned int len, unsigned long *pval) +{ + struct vvtd *vvtd = vcpu_vvtd(v); + unsigned int offset = addr - vvtd->base_addr; + unsigned int offset_aligned = offset & ~3; + + if ( !pval ) + return X86EMUL_OKAY; + + VVTD_DEBUG(VVTD_DBG_RW, "READ INFO: offset %x len %d.", offset, len); + + if ( len != 1 && (offset & 3) != 0 ) + { + VVTD_DEBUG(VVTD_DBG_RW, "Alignment is not canonical."); + return X86EMUL_OKAY; + } + + switch( len ) + { + case 1: + *pval = vvtd_get_reg_byte(vvtd, offset); + break; + + case 4: + *pval = vvtd_get_reg(vvtd, offset_aligned); + break; + + case 8: + vvtd_get_reg_quad(vvtd, offset_aligned, *pval); + break; + + default: + break; + } + + return X86EMUL_OKAY; +} + +static int vvtd_write(struct vcpu *v, unsigned long addr, + unsigned int len, unsigned long val) +{ + struct vvtd *vvtd = vcpu_vvtd(v); + unsigned int offset = addr - vvtd->base_addr; + unsigned int offset_aligned = offset & ~0x3; + unsigned long val_lo = (val & ((1ULL << 32) - 1)); + int ret; + + VVTD_DEBUG(VVTD_DBG_RW, "WRITE INFO: offset %x len %d val %lx.", + offset, len, val); + + if ( offset & 3 ) + { + VVTD_DEBUG(VVTD_DBG_RW, "Alignment is not canonical"); + goto error; + } + + if ( len != 4 && len != 8) + { + VVTD_DEBUG(VVTD_DBG_RW, "Len is not canonical"); + goto error; + } + + ret = X86EMUL_UNHANDLEABLE; + switch ( offset_aligned ) + { + case DMAR_IEDATA_REG: + case DMAR_IEADDR_REG: + case DMAR_IEUADDR_REG: + case DMAR_FEDATA_REG: + case DMAR_FEADDR_REG: + case DMAR_FEUADDR_REG: + if ( len == 8 ) + goto error; + vvtd_set_reg(vvtd, offset_aligned, val_lo); + ret = X86EMUL_OKAY; + break; + + default: + break; + } + +error: + return X86EMUL_OKAY; +} + +static const struct hvm_mmio_ops vvtd_mmio_ops = { + .check = vvtd_range, + .read = vvtd_read, + .write = vvtd_write +}; + static void vvtd_reset(struct vvtd *vvtd, uint64_t capability) { uint64_t cap, ecap; @@ -132,6 +266,7 @@ static struct vvtd *__vvtd_create(struct domain *d, vvtd->base_addr = base_addr; vvtd->domain = d; vvtd->status = 0; + register_mmio_handler(d, &vvtd_mmio_ops); return vvtd; out2: