From patchwork Sat Apr 1 13:53:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9657939 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A68760349 for ; Sat, 1 Apr 2017 13:55:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70C06285C2 for ; Sat, 1 Apr 2017 13:55:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65A0F28610; Sat, 1 Apr 2017 13:55:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F01DD285C2 for ; Sat, 1 Apr 2017 13:55:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cuJU5-0006BI-JX; Sat, 01 Apr 2017 13:54:29 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cuJU4-000691-PV for xen-devel@lists.xenproject.org; Sat, 01 Apr 2017 13:54:28 +0000 Received: from [85.158.137.68] by server-6.bemta-3.messagelabs.com id C6/F0-08534-411BFD85; Sat, 01 Apr 2017 13:54:28 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRWlGSWpSXmKPExsXS1tYhoiu88X6 EwedeWYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNePDyylMBU+1Klr2NrE0MD5V6GLk4mARuMUk cWlBFzOIIyQwjVFi/dorjF2MnBwSArwSR5bNYIWw/SW+3vnBAmILCdRLbN93FcxmE1CXePy1h wnEFhFQkri3ajITyCBmgZ1MEutOf2cGSQgLeEpcbtsAVsQioCrx/sMmsAW8QPHrf/+xQSyQkz h5bDLYMk6g+JUX+6CWeUismnSJeQIj3wJGhlWMGsWpRWWpRbqGFnpJRZnpGSW5iZk5uoYGxnq 5qcXFiempOYlJxXrJ+bmbGIGhUs/AwLiD8fdpz0OMkhxMSqK834vvRQjxJeWnVGYkFmfEF5Xm pBYfYpTh4FCS4FXYcD9CSLAoNT21Ii0zBxi0MGkJDh4lEd5j64HSvMUFibnFmekQqVOMilLiv KkgfQIgiYzSPLg2WKRcYpSVEuZlZGBgEOIpSC3KzSxBlX/FKM7BqCTMKw8yniczrwRu+iugxU xAiy2+3gVZXJKIkJJqYHT4KVgQ2O/V19SRNJEt/rbG40m/f7/mzmjicfdo5zGp6375dZ+C5yf /9rPGfXHTz0/c8smLxXKSrpSqwBX/u5dMZf6tLLX4t6J0iqiSzqNl7nzKvsrzgjrmfb+ud7Xu rdiruskOeV1B2Z5Kvz++LN/1NvJh37EFkincSqnLnRYLONWseiiprMRSnJFoqMVcVJwIABcYo MiPAgAA X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-9.tower-31.messagelabs.com!1491054811!37933881!19 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 55061 invoked from network); 1 Apr 2017 13:54:27 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-9.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 1 Apr 2017 13:54:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491054867; x=1522590867; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=lKfJ1c1mvDX4vrs9FccakevRqA0mxQWwbmPG560HzCE=; b=rkninHOYYyE0QqjEgweioPzznM13Nxgv61b6jWSArLiqGHkm36mHJI4Z Iho9XY9XxZJaC7fmqxxmMiFzp33Jsg==; Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2017 06:54:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,258,1486454400"; d="scan'208";a="950545208" Received: from yisun1-ubuntu.bj.intel.com ([10.238.156.112]) by orsmga003.jf.intel.com with ESMTP; 01 Apr 2017 06:54:23 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Sat, 1 Apr 2017 21:53:49 +0800 Message-Id: <1491054836-30488-19-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491054836-30488-1-git-send-email-yi.y.sun@linux.intel.com> References: <1491054836-30488-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v10 18/25] x86: L2 CAT: implement CPU init and free flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init and free flow for L2 CAT. Signed-off-by: Yi Sun --- v10: - implement L2 CAT case in 'cat_init_feature'. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - introduce 'PSR_CBM_TYPE_L2'. v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 33 +++++++++++++++++++++++++++++++-- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 ++ 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index bfa1777..6a9cd88 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -160,6 +160,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3_cat; static struct feat_node *feat_l3_cdp; +static struct feat_node *feat_l2_cat; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf *regs, switch ( type ) { case PSR_SOCKET_L3_CAT: + case PSR_SOCKET_L2_CAT: /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len); - feat->props->type[0] = PSR_CBM_TYPE_L3; + if ( type == PSR_SOCKET_L3_CAT ) + feat->props->type[0] = PSR_CBM_TYPE_L3; + else + feat->props->type[0] = PSR_CBM_TYPE_L2; /* * To handle cpu offline and then online case, we need restore MSRs to @@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs, */ for ( i = 1; i <= feat->props->cos_max; i++ ) { - wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); + if ( type == PSR_SOCKET_L3_CAT ) + wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); + else + wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]); + feat->cos_reg_val[i] = feat->cos_reg_val[0]; } @@ -454,6 +463,11 @@ static struct feat_props l3_cdp_props = { .write_msr = l3_cdp_write_msr, }; +/* L2 CAT ops */ +static struct feat_props l2_cat_props = { + .cos_num = 1, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1393,6 +1407,10 @@ static int psr_cpu_prepare(void) (feat_l3_cdp = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2_cat == NULL && + (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1442,6 +1460,17 @@ static void psr_cpu_init(void) } } + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); + + feat = feat_l2_cat; + feat_l2_cat = NULL; + feat->props = &l2_cat_props; + cat_init_feature(®s, feat, info, PSR_SOCKET_L2_CAT); + } + assoc_init: psr_assoc_init(); } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 771e750..6c49c6d 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -345,6 +345,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index 66d5218..e576f27 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -56,6 +57,7 @@ enum cbm_type { PSR_CBM_TYPE_L3, PSR_CBM_TYPE_L3_CODE, PSR_CBM_TYPE_L3_DATA, + PSR_CBM_TYPE_L2, }; extern struct psr_cmt *psr_cmt;