From patchwork Wed May 3 08:44:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9709029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 11B7E60385 for ; Wed, 3 May 2017 08:56:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E760828602 for ; Wed, 3 May 2017 08:56:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DC12F28606; Wed, 3 May 2017 08:56:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A1D028602 for ; Wed, 3 May 2017 08:56:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d5q37-0000pZ-EP; Wed, 03 May 2017 08:54:17 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d5q36-0000ny-2c for xen-devel@lists.xenproject.org; Wed, 03 May 2017 08:54:16 +0000 Received: from [85.158.139.211] by server-4.bemta-5.messagelabs.com id A8/20-02181-7BA99095; Wed, 03 May 2017 08:54:15 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRWlGSWpSXmKPExsXS1tYhobttFme kwbvN+hbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8baF4eZCl5ZVuzd8JOlgfGLVhcjF4eQwHRG iekrOpm6GDk5JAR4JY4sm8EKYftLNHy7zAJR1MAocfL+A0aQBJuAusTjrz1gDSICShL3Vk1mA iliFtjJJLHu9HdmkISwgLfE1wfLwIpYBFQl/l7YBGbzCnhKTPtxgRlig5zEyWOTwbZxAsWff9 nIDmILCXhIHHr2nmkCI+8CRoZVjOrFqUVlqUW6xnpJRZnpGSW5iZk5uoYGpnq5qcXFiempOYl JxXrJ+bmbGIEBwQAEOxj3/nM6xCjJwaQkyqv+ij1SiC8pP6UyI7E4I76oNCe1+BCjDAeHkgTv w5mckUKCRanpqRVpmTnA0IRJS3DwKInwdoGkeYsLEnOLM9MhUqcYdTn6Oj6+ZxJiycvPS5US5 50OUiQAUpRRmgc3AhYnlxhlpYR5GYGOEuIpSC3KzSxBlX/FKM7BqCTMmwwyhSczrwRu0yugI5 iAjmiW5QA5oiQRISXVwLjsevG7Bm6d3RfMLQy2XzjBl/Lse+udz38FiqW80+NrT8faL6z2T1L mnbajb/reoksia34wcMizH2ddbLVh89WU/J7zhgYWmi1ONccuzTtglrHtgcwh1gO7LjmxFx8t Ot42r2bRDvVLRWcaj5syvP2f06n7p6lC5PMDD61/Z57s+LFcfeH6c0eVWIozEg21mIuKEwFCU VrwjgIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-2.tower-206.messagelabs.com!1493801620!75519330!14 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11395 invoked from network); 3 May 2017 08:54:14 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-2.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 3 May 2017 08:54:14 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 May 2017 01:54:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,283,1491289200"; d="scan'208";a="852347641" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.39]) by FMSMGA003.fm.intel.com with ESMTP; 03 May 2017 01:54:11 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Wed, 3 May 2017 16:44:13 +0800 Message-Id: <1493801063-38513-14-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493801063-38513-1-git-send-email-yi.y.sun@linux.intel.com> References: <1493801063-38513-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init flow for CDP. The flow is almost same as L3 CAT. Signed-off-by: Yi Sun --- v11: - changes about 'feat_props'. (suggested by Jan Beulich) - remove MSR restore action which is unnecessary. (suggested by Jan Beulich) - modify commit message. v10: - fix comment. (suggested by Jan Beulich) - use swith in 'cat_init_feature' to handle different feature types. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - restore MSRs to default value when cpu online. (suggested by Jan Beulich) - remove feat_mask. (suggested by Jan Beulich) v9: - modify commit message to describe flow clearer. - handle cpu offline and online again case to read MSRs registers values back and save them into cos array to make user can get real data. - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - modify 'get_cdp_data' and 'get_cdp_code' to make them standard. (suggested by Roger Pau and Jan Beulich) - encapsulate CDP operations into 'cat_init_feature' to reduce redundant codes. (suggested by Roger Pau) - reuse 'cat_get_cos_max' for CDP. (suggested by Roger Pau) - handle 'PSR_CDP' in psr_presmp_init to make init work can be done when there is only 'psr=cdp' in cmdline. - remove unnecessary comment. (suggested by Jan Beulich) - move CDP related codes in 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - add codes to handle CDP's 'cos_num'. (suggested by Jan Beulich) - fix coding style issue. (suggested by Jan Beulich) - do not free resources when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) - changes about 'uint64_t' to 'uint32_t'. (suggested by Jan Beulich) v7: - initialize 'l3_cdp'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove codes to free 'feat_l3_cdp' in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]'. (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch to make codes easier to understand. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 68 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 9b8428d..7000d95 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -62,6 +62,7 @@ enum psr_feat_type { PSR_SOCKET_L3_CAT, + PSR_SOCKET_L3_CDP, PSR_SOCKET_FEAT_NUM, PSR_SOCKET_FEAT_UNKNOWN, }; @@ -150,11 +151,28 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); * array creation. It is used to transiently store a spare node. */ static struct feat_node *feat_l3_cat; +static struct feat_node *feat_l3_cdp; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) /* + * get_cdp_data - get DATA COS register value from input COS ID. + * @feat: the feature node. + * @cos: the COS ID. + */ +#define get_cdp_data(feat, cos) \ + ( (feat)->cos_reg_val[(cos) * 2] ) + +/* + * get_cdp_code - get CODE COS register value from input COS ID. + * @feat: the feature node. + * @cos: the COS ID. + */ +#define get_cdp_code(feat, cos) \ + ( (feat)->cos_reg_val[(cos) * 2 + 1] ) + +/* * Use this function to check if any allocation feature has been enabled * in cmdline. */ @@ -249,6 +267,25 @@ static void cat_init_feature(const struct cpuid_leaf *regs, break; + case PSR_SOCKET_L3_CDP: + { + unsigned long val; + + /* Cut half of cos_max when CDP is enabled. */ + feat->cos_max >>= 1; + + /* We only write mask1 since mask0 is always all ones by default. */ + wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len)); + rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val); + wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT)); + + /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ + get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len); + get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len); + + break; + } + default: return; } @@ -259,8 +296,9 @@ static void cat_init_feature(const struct cpuid_leaf *regs, if ( !opt_cpu_info ) return; - printk(XENLOG_INFO "%s CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n", - ((type == PSR_SOCKET_L3_CAT) ? "L3" : "L2"), + printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", + ((type == PSR_SOCKET_L3_CDP) ? "CDP" : + ((type == PSR_SOCKET_L3_CAT) ? "L3 CAT": "L2 CAT")), cpu_to_socket(smp_processor_id()), feat->cos_max, feat->cbm_len); } @@ -289,6 +327,11 @@ static struct feat_props l3_cat_props = { .write_msr = l3_cat_write_msr, }; +/* L3 CDP props */ +static struct feat_props l3_cdp_props = { + .cos_num = 2, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1206,6 +1249,10 @@ static int psr_cpu_prepare(void) (feat_l3_cat = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l3_cdp == NULL && + (feat_l3_cdp = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1238,12 +1285,24 @@ static void psr_cpu_init(void) { cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s); - feat = feat_l3_cat; - feat_l3_cat = NULL; - l3_cat_props.type[0] = PSR_CBM_TYPE_L3; - feat_props[PSR_SOCKET_L3_CAT] = &l3_cat_props; - - cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CAT); + if ( (regs.c & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) && + !info->features[PSR_SOCKET_L3_CDP] ) + { + feat = feat_l3_cdp; + feat_l3_cdp = NULL; + l3_cdp_props.type[0] = PSR_CBM_TYPE_L3_DATA; + l3_cdp_props.type[1] = PSR_CBM_TYPE_L3_CODE; + feat_props[PSR_SOCKET_L3_CDP] = &l3_cdp_props; + cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CDP); + } + else + { + feat = feat_l3_cat; + feat_l3_cat = NULL; + l3_cat_props.type[0] = PSR_CBM_TYPE_L3; + feat_props[PSR_SOCKET_L3_CAT] = &l3_cat_props; + cat_init_feature(®s, feat, info, PSR_SOCKET_L3_CAT); + } info->feat_init = true; } @@ -1305,7 +1364,7 @@ static int __init psr_presmp_init(void) if ( (opt_psr & PSR_CMT) && opt_rmid_max ) init_psr_cmt(opt_rmid_max); - if ( opt_psr & PSR_CAT ) + if ( opt_psr & (PSR_CAT | PSR_CDP) ) init_psr(); if ( psr_cpu_prepare() )