From patchwork Wed May 3 08:44:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9709023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D71F60385 for ; Wed, 3 May 2017 08:56:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3B1F28604 for ; Wed, 3 May 2017 08:56:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D898528608; Wed, 3 May 2017 08:56:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3AC9628606 for ; Wed, 3 May 2017 08:56:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d5q2o-0000Xz-Hm; Wed, 03 May 2017 08:53:58 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1d5q2n-0000XP-FD for xen-devel@lists.xenproject.org; Wed, 03 May 2017 08:53:57 +0000 Received: from [85.158.139.211] by server-10.bemta-5.messagelabs.com id 4E/DD-01734-4AA99095; Wed, 03 May 2017 08:53:56 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDLMWRWlGSWpSXmKPExsXS1tYhobtwFme kwdNWFovvWyYzOTB6HP5whSWAMYo1My8pvyKBNePF5/tMBTc0KzYtb2JpYDwq38XIxSEkMJ1R YvrDicxdjJwcEgK8EkeWzWDtYmQHsv0ljniDRIUEGhglVr0TBbHZBNQlHn/tYQKxRQSUJO6tm swEMoZZYCeTxLrT38HGCAukSFw/0MoKYrMIqEr0tcxlAbF5BTwk7m7/yQqxSk7i5LHJYDangK fE8y8b2SGWeUgcevaeaQIj7wJGhlWM6sWpRWWpRbrGeklFmekZJbmJmTm6hgamermpxcWJ6ak 5iUnFesn5uZsYgaHAAAQ7GPf+czrEKMnBpCTKq/6KPVKILyk/pTIjsTgjvqg0J7X4EKMMB4eS BO/DmZyRQoJFqempFWmZOcCghElLcPAoifB2gaR5iwsSc4sz0yFSpxgVpcR5p4MkBEASGaV5c G2wSLjEKCslzMsIdIgQT0FqUW5mCar8K0ZxDkYlYd5kkCk8mXklcNNfAS1mAlrcLMsBsrgkES El1cAoGXwiPzE0O+7Ru/1ON4Q585Y9yTX9bzvz5w8fvu9HMiJt5ATEVY0mnDnV+otjapBr6jn mlNac8hdGNyc/+N+pXzfneP2a/SKibPWnust8btys4bp8YLuDU7ioQJfCk+5q5esH3Ree/ujg 1eajOr38x8b9jv0rP/hLW/TPVZ/9+fERM1u9SzFKLMUZiYZazEXFiQDNGWWlfwIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-2.tower-206.messagelabs.com!1493801620!75519330!6 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7206 invoked from network); 3 May 2017 08:53:52 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-2.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 3 May 2017 08:53:52 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 May 2017 01:53:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,283,1491289200"; d="scan'208";a="852347550" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.39]) by FMSMGA003.fm.intel.com with ESMTP; 03 May 2017 01:53:49 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Wed, 3 May 2017 16:44:05 +0800 Message-Id: <1493801063-38513-6-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493801063-38513-1-git-send-email-yi.y.sun@linux.intel.com> References: <1493801063-38513-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v11 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the Domain init/free and schedule flows. - When domain init, its psr resource should be allocated. - When domain free, its psr resource should be freed too. - When domain is scheduled, its COS ID on the socket should be set into ASSOC register to make corresponding COS MSR value work. Signed-off-by: Yi Sun --- v11: - replace 'feat_init_done()' to 'feat_init' flag. (suggested by Jan Beulich) - adjust parameters positions when calling 'psr_assoc_cos'. (suggested by Jan Beulich) - add comment to explain why to check 'psr_cos_ids'. v10: - remove 'cat_get_cos_max' as 'cos_max' is a feature property now which can be directly used. (suggested by Jan Beulich) - replace 'info->feat_mask' check to 'feat_init_done'. (suggested by Jan Beulich) v9: - rename 'l3_cat_get_cos_max' to 'cat_get_cos_max' to cover all CAT/CDP features. (suggested by Roger Pau) - replace feature list handling to feature array handling. (suggested by Roger Pau) - implement 'psr_alloc_cos' to match 'psr_free_cos'. (suggested by Wei Liu) - use 'psr_alloc_feat_enabled'. (suggested by Wei Liu) - fix coding style issue. (suggested by Wei Liu) - remove 'inline'. (suggested by Jan Beulich) - modify patch title to indicate 'L3 CAT'. (suggested by Jan Beulich) - remove 'psr_cos_ids' check in 'psr_free_cos'. (suggested by Jan Beulich) v6: - change 'PSR_ASSOC_REG_POS' to 'PSR_ASSOC_REG_SHIFT'. (suggested by Konrad Rzeszutek Wilk) v5: - rename 'feat_tmp' to 'feat'. (suggested by Jan Beulich) - define 'PSR_ASSOC_REG_POS'. (suggested by Jan Beulich) v4: - create this patch to make codes easier to understand. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index b73856e..bda325d 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -50,6 +50,8 @@ */ #define MAX_COS_REG_CNT 128 +#define PSR_ASSOC_REG_SHIFT 32 + /* * Every PSR feature uses some COS registers for each COS ID, e.g. CDP uses 2 * COS registers (DATA and CODE) for one COS ID, but CAT uses 1 COS register. @@ -355,11 +357,38 @@ void psr_free_rmid(struct domain *d) d->arch.psr_rmid = 0; } -static inline void psr_assoc_init(void) +static unsigned int get_max_cos_max(const struct psr_socket_info *info) +{ + unsigned int cos_max = 0, i; + + for ( i = 0; i < PSR_SOCKET_FEAT_NUM; i++ ) + { + const struct feat_node *feat = info->features[i]; + if ( !feat ) + continue; + + cos_max = max(feat->cos_max, cos_max); + } + + return cos_max; +} + +static void psr_assoc_init(void) { struct psr_assoc *psra = &this_cpu(psr_assoc); - if ( psr_cmt_enabled() ) + if ( psr_alloc_feat_enabled() ) + { + unsigned int socket = cpu_to_socket(smp_processor_id()); + const struct psr_socket_info *info = socket_info + socket; + unsigned int cos_max = get_max_cos_max(info); + + if ( info->feat_init ) + psra->cos_mask = ((1ull << get_count_order(cos_max)) - 1) << + PSR_ASSOC_REG_SHIFT; + } + + if ( psr_cmt_enabled() || psra->cos_mask ) rdmsrl(MSR_IA32_PSR_ASSOC, psra->val); } @@ -368,6 +397,13 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid) *reg = (*reg & ~rmid_mask) | (rmid & rmid_mask); } +static void psr_assoc_cos(uint64_t *reg, unsigned int cos, + uint64_t cos_mask) +{ + *reg = (*reg & ~cos_mask) | + (((uint64_t)cos << PSR_ASSOC_REG_SHIFT) & cos_mask); +} + void psr_ctxt_switch_to(struct domain *d) { struct psr_assoc *psra = &this_cpu(psr_assoc); @@ -376,6 +412,14 @@ void psr_ctxt_switch_to(struct domain *d) if ( psr_cmt_enabled() ) psr_assoc_rmid(®, d->arch.psr_rmid); + /* IDLE domain's 'psr_cos_ids' is NULL so we set default value for it. */ + if ( psra->cos_mask ) + psr_assoc_cos(®, + d->arch.psr_cos_ids ? + d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] : + 0, + psra->cos_mask); + if ( reg != psra->val ) { wrmsrl(MSR_IA32_PSR_ASSOC, reg); @@ -401,14 +445,37 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket, return 0; } -int psr_domain_init(struct domain *d) +/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */ +static void psr_free_cos(struct domain *d) +{ + xfree(d->arch.psr_cos_ids); + d->arch.psr_cos_ids = NULL; +} + +static int psr_alloc_cos(struct domain *d) { + d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets); + if ( !d->arch.psr_cos_ids ) + return -ENOMEM; + return 0; } +int psr_domain_init(struct domain *d) +{ + /* Init to success value */ + int ret = 0; + + if ( psr_alloc_feat_enabled() ) + ret = psr_alloc_cos(d); + + return ret; +} + void psr_domain_free(struct domain *d) { psr_free_rmid(d); + psr_free_cos(d); } static void __init init_psr(void)