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[85.223.209.54]) by smtp.gmail.com with ESMTPSA id c34sm3378304wrc.7.2017.05.10.07.03.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 May 2017 07:03:38 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Wed, 10 May 2017 17:03:09 +0300 Message-Id: <1494424994-26232-6-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494424994-26232-1-git-send-email-olekstysh@gmail.com> References: <1494424994-26232-1-git-send-email-olekstysh@gmail.com> Cc: wei.liu2@citrix.com, julien.grall@arm.com, sstabellini@kernel.org, ian.jackson@eu.citrix.com, jbeulich@suse.com Subject: [Xen-devel] [PATCH v1 05/10] iommu/arm: Re-define iommu_use_hap_pt(d) as iommu_hap_pt_share X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko Not every integrated into ARM SoCs IOMMU can share page tables with the CPU and as result the iommu_use_hap_pt(d) is not always true. Reuse x86's iommu_hap_pt_share flag to indicate whether the IOMMU page table is shared or not. Now all IOMMU drivers on ARM are able to change this flag according to their possibilities like x86-variants do. Therefore set iommu_hap_pt_share flag for SMMU because it always shares page table with the CPU. Signed-off-by: Oleksandr Tyshchenko --- xen/drivers/passthrough/arm/smmu.c | 3 +++ xen/include/asm-arm/iommu.h | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 527a592..86ee12a 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2870,6 +2870,9 @@ static __init int arm_smmu_dt_init(struct dt_device_node *dev, platform_features &= smmu->features; + /* Always share P2M table between the CPU and the SMMU */ + iommu_hap_pt_share = true; + return 0; } diff --git a/xen/include/asm-arm/iommu.h b/xen/include/asm-arm/iommu.h index 57d9b1e..10a6f23 100644 --- a/xen/include/asm-arm/iommu.h +++ b/xen/include/asm-arm/iommu.h @@ -20,8 +20,11 @@ struct arch_iommu void *priv; }; -/* Always share P2M Table between the CPU and the IOMMU */ -#define iommu_use_hap_pt(d) (1) +/* + * The ARM domain always has a P2M table, but not every integrated into + * ARM SoCs IOMMU can use it as page table. + */ +#define iommu_use_hap_pt(d) (iommu_hap_pt_share) const struct iommu_ops *iommu_get_ops(void); void __init iommu_set_ops(const struct iommu_ops *ops);