From patchwork Thu May 18 05:34:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9733855 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C09F3601BC for ; Thu, 18 May 2017 11:42:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B03A420952 for ; Thu, 18 May 2017 11:42:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A512B25404; Thu, 18 May 2017 11:42:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 54C1E20952 for ; Thu, 18 May 2017 11:42:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJna-0004ut-Pv; Thu, 18 May 2017 11:40:54 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnY-0004rV-Tq for xen-devel@lists.xen.org; Thu, 18 May 2017 11:40:53 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id 6E/77-01992-4488D195; Thu, 18 May 2017 11:40:52 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRWlGSWpSXmKPExsVywNykWNe5Qzb S4MsyBYslHxezODB6HN39mymAMYo1My8pvyKBNePa8kdMBT+EKrYcP8fewHiCv4uRi0NIYDqj ROfuP6xdjJwcEgK8EkeWzYCyAyRezl7ABFHUwSjR/XsHO0iCTUBd4sTiiYwgtoiAtMS1z5fBb GaBfYwSb56rgtjCAv4Sfz4/ZQOxWQRUJf60nQWr4RVwlWjc8JMFYoGCxJSH75lBbE6g+Latt8 DiQgIuEo0Le1knMPIuYGRYxahRnFpUllqka2iol1SUmZ5RkpuYmaNraGCql5taXJyYnpqTmFS sl5yfu4kRGBAMQLCDcWW78yFGSQ4mJVHewwWykUJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkePna gXKCRanpqRVpmTnA0IRJS3DwKInw6oCkeYsLEnOLM9MhUqcYFaXEeTe2ASUEQBIZpXlwbbB4u MQoKyXMywh0iBBPQWpRbmYJqvwrRnEORiVhXlaQ8TyZeSVw018BLWYCWtz8QBpkcUkiQkqqgZ HN7/uGJ/8+Fb9/N2lKZJ+YkGrM904Wy5NhH08cYph9Y1uDiNeZ2yvOiuYqPWEv1VoelMe/cbF NUvofpmq2CuWjV8X+m11T2/nL6YejYdipl8vWRM59kW1T6Zx+atOelQuWu4qEb+sRZUhJC5GM f/lueunByhkbZsvbbNme8/SWqLf3DRbhdypKLMUZiYZazEXFiQCoyvMWggIAAA== X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1495107647!84949287!1 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.8 required=7.0 tests=DATE_IN_PAST_06_12 X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9991 invoked from network); 18 May 2017 11:40:50 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-15.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 18 May 2017 11:40:50 -0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 May 2017 04:40:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,358,1491289200"; d="scan'208"; a="1171087859" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.124]) by fmsmga002.fm.intel.com with ESMTP; 18 May 2017 04:40:45 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 18 May 2017 01:34:47 -0400 Message-Id: <1495085696-10819-18-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> References: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, Chao Gao Subject: [Xen-devel] [RFC PATCH V2 17/26] X86/vvtd: Enable Queued Invalidation through GCMD X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao Software writes to QIE fields of GCMD to enable or disable queued invalidations. This patch emulates QIE fields of GCMD. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/arch/x86/hvm/vvtd.c | 18 ++++++++++++++++++ xen/drivers/passthrough/vtd/iommu.h | 3 ++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vvtd.c b/xen/arch/x86/hvm/vvtd.c index 57932cb..be3acd5 100644 --- a/xen/arch/x86/hvm/vvtd.c +++ b/xen/arch/x86/hvm/vvtd.c @@ -102,6 +102,11 @@ static inline void __vvtd_set_bit(struct vvtd *vvtd, uint32_t reg, int nr) return __set_bit(nr, (uint32_t *)&vvtd->regs->data[reg]); } +static inline void __vvtd_clear_bit(struct vvtd *vvtd, uint32_t reg, int nr) +{ + return __clear_bit(nr, (uint32_t *)&vvtd->regs->data[reg]); +} + static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg, uint32_t value) { @@ -262,6 +267,17 @@ static int vvtd_record_fault(struct vvtd *vvtd, return 0; } +static int vvtd_handle_gcmd_qie(struct vvtd *vvtd, uint32_t val) +{ + VVTD_DEBUG(VVTD_DBG_RW, "Enable Queue Invalidation."); + + if ( val & DMA_GCMD_QIE ) + __vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_QIES_BIT); + else + __vvtd_clear_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_QIES_BIT); + return X86EMUL_OKAY; +} + static int vvtd_handle_gcmd_sirtp(struct vvtd *vvtd, uint32_t val) { uint64_t irta; @@ -293,6 +309,8 @@ static int vvtd_write_gcmd(struct vvtd *vvtd, uint32_t val) if ( changed & DMA_GCMD_SIRTP ) vvtd_handle_gcmd_sirtp(vvtd, val); + if ( changed & DMA_GCMD_QIE ) + vvtd_handle_gcmd_qie(vvtd, val); return X86EMUL_OKAY; } diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 1c53d22..2d60df6 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -193,7 +193,8 @@ #define DMA_GSTS_FLS (((u64)1) << 29) #define DMA_GSTS_AFLS (((u64)1) << 28) #define DMA_GSTS_WBFS (((u64)1) << 27) -#define DMA_GSTS_QIES (((u64)1) <<26) +#define DMA_GSTS_QIES_BIT 26 +#define DMA_GSTS_QIES (((u64)1) << DMA_GSTS_QIES_BIT) #define DMA_GSTS_IRES (((u64)1) <<25) #define DMA_GSTS_SIRTPS_BIT 24 #define DMA_GSTS_SIRTPS (((u64)1) << DMA_GSTS_SIRTPS_BIT)