From patchwork Thu May 18 05:34:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9733891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B91B9601BC for ; Thu, 18 May 2017 11:42:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A825620952 for ; Thu, 18 May 2017 11:42:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9CD642621D; Thu, 18 May 2017 11:42:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F1F0120952 for ; Thu, 18 May 2017 11:42:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnr-0005NC-Ov; Thu, 18 May 2017 11:41:11 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnq-0005K3-BN for xen-devel@lists.xen.org; Thu, 18 May 2017 11:41:10 +0000 Received: from [85.158.143.35] by server-4.bemta-6.messagelabs.com id 69/00-02956-5588D195; Thu, 18 May 2017 11:41:09 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRWlGSWpSXmKPExsVywNwkQje0Qzb S4MEKAYslHxezODB6HN39mymAMYo1My8pvyKBNeP+pyvsBbstKw7tO8/ewLhQt4uRi0NIYDqj xLm/O1m6GDk5JAR4JY4sm8EKYQdI7HyzixHEFhLoYJT4OksIxGYTUJc4sXgiWFxEQFri2ufLj CCDmAV6GCUmLnsENkhYwE1i57NWsCIWAVWJNavPgNm8Aq4SJ1d2MkEsUJCY8vA9M4jNCRTftv UWC8QyF4nGhb2sExh5FzAyrGJUL04tKkst0rXQSyrKTM8oyU3MzNE1NDDTy00tLk5MT81JTCr WS87P3cQIDAcGINjBOPuy/yFGSQ4mJVHewwWykUJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkeDe0 AeUEi1LTUyvSMnOAgQmTluDgURLhXQOS5i0uSMwtzkyHSJ1i1OV4t/TDeyYhlrz8vFQpcd6NI EUCIEUZpXlwI2BRcolRVkqYlxHoKCGegtSi3MwSVPlXjOIcjErCvMdApvBk5pXAbXoFdAQT0B HND6RBjihJREhJNTDWNNy4zNO2zHiHb69ac45Q4j6Hp5pzFN+nJChOrJA6ruvYfHzyH+kyA5s KJ/2sw28+b3l8N6pb5OV/0RsWXFYL+r4abPw9baXeZ27BlDcZ/pvmr/6e8sh+quP8rSvvTP69 LiNvf6PXiyl6/x9/PCI+dcbRpewFahKL/T5fvea9RE/493u/ejFHJZbijERDLeai4kQARBn2j o0CAAA= X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1495107667!64824476!1 X-Originating-IP: [192.55.52.88] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjg4ID0+IDM3NDcyNQ==\n X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24715 invoked from network); 18 May 2017 11:41:08 -0000 Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by server-16.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 18 May 2017 11:41:08 -0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 May 2017 04:41:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,358,1491289200"; d="scan'208"; a="1171088049" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.124]) by fmsmga002.fm.intel.com with ESMTP; 18 May 2017 04:41:04 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 18 May 2017 01:34:56 -0400 Message-Id: <1495085696-10819-27-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> References: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , andrew.cooper3@citrix.com, kevin.tian@intel.com, jbeulich@suse.com, Chao Gao Subject: [Xen-devel] [RFC PATCH V2 26/26] x86/vvtd: save and restore emulated VT-d X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao Wrap some useful status in a new structure hvm_hw_vvtd, following the customs of vlapic, vioapic and etc. Provide two save-restore pairs to save/restore registers and non-register status. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/arch/x86/hvm/vvtd.c | 98 ++++++++++++++++++++++------------ xen/include/public/arch-x86/hvm/save.h | 24 ++++++++- 2 files changed, 88 insertions(+), 34 deletions(-) diff --git a/xen/arch/x86/hvm/vvtd.c b/xen/arch/x86/hvm/vvtd.c index ce25a77..e35bc9e 100644 --- a/xen/arch/x86/hvm/vvtd.c +++ b/xen/arch/x86/hvm/vvtd.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -33,38 +34,25 @@ #include #include #include +#include #include "../../../drivers/passthrough/vtd/iommu.h" #include "../../../drivers/passthrough/vtd/vtd.h" -struct hvm_hw_vvtd_regs { - uint8_t data[1024]; -}; - /* Status field of struct vvtd */ #define VIOMMU_STATUS_IRQ_REMAPPING_ENABLED (1 << 0) #define VIOMMU_STATUS_DMA_REMAPPING_ENABLED (1 << 1) #define vvtd_irq_remapping_enabled(vvtd) \ - (vvtd->status & VIOMMU_STATUS_IRQ_REMAPPING_ENABLED) + (vvtd->hw.status & VIOMMU_STATUS_IRQ_REMAPPING_ENABLED) struct vvtd { - /* VIOMMU_STATUS_XXX_REMAPPING_ENABLED */ - int status; - /* Fault Recording index */ - int frcd_idx; /* Address range of remapping hardware register-set */ uint64_t base_addr; uint64_t length; /* Point back to the owner domain */ struct domain *domain; - /* Is in Extended Interrupt Mode? */ - bool eim; - /* Max remapping entries in IRT */ - int irt_max_entry; - /* Interrupt remapping table base gfn */ - uint64_t irt; - + struct hvm_hw_vvtd hw; struct hvm_hw_vvtd_regs *regs; struct page_info *regs_page; }; @@ -369,12 +357,12 @@ static int vvtd_alloc_frcd(struct vvtd *vvtd) { int prev; /* Set the F bit to indicate the FRCD is in use. */ - if ( vvtd_test_and_set_bit(vvtd, DMA_FRCD(vvtd->frcd_idx, DMA_FRCD3_OFFSET), + if ( vvtd_test_and_set_bit(vvtd, DMA_FRCD(vvtd->hw.frcd_idx, DMA_FRCD3_OFFSET), DMA_FRCD_F_BIT) ) { - prev = vvtd->frcd_idx; - vvtd->frcd_idx = (prev + 1) % DMAR_FRCD_REG_NR; - return vvtd->frcd_idx; + prev = vvtd->hw.frcd_idx; + vvtd->hw.frcd_idx = (prev + 1) % DMAR_FRCD_REG_NR; + return vvtd->hw.frcd_idx; } return -1; } @@ -706,12 +694,12 @@ static int vvtd_handle_gcmd_ire(struct vvtd *vvtd, uint32_t val) if ( val & DMA_GCMD_IRE ) { - vvtd->status |= VIOMMU_STATUS_IRQ_REMAPPING_ENABLED; + vvtd->hw.status |= VIOMMU_STATUS_IRQ_REMAPPING_ENABLED; __vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_IRES_BIT); } else { - vvtd->status |= ~VIOMMU_STATUS_IRQ_REMAPPING_ENABLED; + vvtd->hw.status |= ~VIOMMU_STATUS_IRQ_REMAPPING_ENABLED; __vvtd_clear_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_IRES_BIT); } @@ -730,11 +718,11 @@ static int vvtd_handle_gcmd_sirtp(struct vvtd *vvtd, uint32_t val) "active." ); vvtd_get_reg_quad(vvtd, DMAR_IRTA_REG, irta); - vvtd->irt = DMA_IRTA_ADDR(irta) >> PAGE_SHIFT; - vvtd->irt_max_entry = DMA_IRTA_SIZE(irta); - vvtd->eim = DMA_IRTA_EIME(irta); + vvtd->hw.irt = DMA_IRTA_ADDR(irta) >> PAGE_SHIFT; + vvtd->hw.irt_max_entry = DMA_IRTA_SIZE(irta); + vvtd->hw.eim = DMA_IRTA_EIME(irta); VVTD_DEBUG(VVTD_DBG_RW, "Update IR info (addr=%lx eim=%d size=%d).", - vvtd->irt, vvtd->eim, vvtd->irt_max_entry); + vvtd->hw.irt, vvtd->hw.eim, vvtd->hw.irt_max_entry); __vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_SIRTPS_BIT); return X86EMUL_OKAY; @@ -953,13 +941,13 @@ static int vvtd_get_entry(struct vvtd *vvtd, VVTD_DEBUG(VVTD_DBG_TRANS, "interpret a request with index %x", entry); - if ( entry > vvtd->irt_max_entry ) + if ( entry > vvtd->hw.irt_max_entry ) { ret = VTD_FR_IR_INDEX_OVER; goto handle_fault; } - ret = map_guest_page(vvtd->domain, vvtd->irt + (entry >> IREMAP_ENTRY_ORDER), + ret = map_guest_page(vvtd->domain, vvtd->hw.irt + (entry >> IREMAP_ENTRY_ORDER), (void**)&irt_page); if ( ret ) { @@ -1084,6 +1072,49 @@ static int vvtd_get_irq_info(struct domain *d, return 0; } +static int vvtd_load_regs(struct domain *d, hvm_domain_context_t *h) +{ + if ( !domain_vvtd(d) ) + return -ENODEV; + + if ( hvm_load_entry(IOMMU_REGS, h, domain_vvtd(d)->regs) ) + return -EINVAL; + + return 0; +} + +static int vvtd_save_regs(struct domain *d, hvm_domain_context_t *h) +{ + if ( !domain_vvtd(d) ) + return 0; + + return hvm_save_entry(IOMMU_REGS, 0, h, domain_vvtd(d)->regs); +} + +static int vvtd_load_hidden(struct domain *d, hvm_domain_context_t *h) +{ + if ( !domain_vvtd(d) ) + return -ENODEV; + + if ( hvm_load_entry(IOMMU, h, &domain_vvtd(d)->hw) ) + return -EINVAL; + + return 0; +} + +static int vvtd_save_hidden(struct domain *d, hvm_domain_context_t *h) +{ + if ( !domain_vvtd(d) ) + return 0; + + return hvm_save_entry(IOMMU, 0, h, &domain_vvtd(d)->hw); +} + +HVM_REGISTER_SAVE_RESTORE(IOMMU, vvtd_save_hidden, vvtd_load_hidden, + 1, HVMSR_PER_DOM); +HVM_REGISTER_SAVE_RESTORE(IOMMU_REGS, vvtd_save_regs, vvtd_load_regs, + 1, HVMSR_PER_DOM); + static void vvtd_reset(struct vvtd *vvtd, uint64_t capability) { uint64_t cap, ecap; @@ -1147,12 +1178,13 @@ static int vvtd_create(struct domain *d, struct viommu *viommu) vvtd->base_addr = viommu->base_address; vvtd->length = viommu->length; vvtd->domain = d; - vvtd->status = 0; - vvtd->eim = 0; - vvtd->irt = 0; - vvtd->irt_max_entry = 0; - vvtd->frcd_idx = 0; + vvtd->hw.status = 0; + vvtd->hw.eim = 0; + vvtd->hw.irt = 0; + vvtd->hw.irt_max_entry = 0; + vvtd->hw.frcd_idx = 0; register_mmio_handler(d, &vvtd_mmio_ops); + viommu->priv = (void *)vvtd; return 0; out2: diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 816973b..28fafc8 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -638,10 +638,32 @@ struct hvm_msr { #define CPU_MSR_CODE 20 +struct hvm_hw_vvtd_regs { + uint8_t data[1024]; +}; + +DECLARE_HVM_SAVE_TYPE(IOMMU_REGS, 21, struct hvm_hw_vvtd_regs); + +struct hvm_hw_vvtd +{ + /* VIOMMU_STATUS_XXX_REMAPPING_ENABLED */ + uint32_t status; + /* Fault Recording index */ + uint32_t frcd_idx; + /* Is in Extended Interrupt Mode? */ + uint32_t eim; + /* Max remapping entries in IRT */ + uint32_t irt_max_entry; + /* Interrupt remapping table base gfn */ + uint64_t irt; +}; + +DECLARE_HVM_SAVE_TYPE(IOMMU, 22, struct hvm_hw_vvtd); + /* * Largest type-code in use */ -#define HVM_SAVE_CODE_MAX 20 +#define HVM_SAVE_CODE_MAX 22 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */