From patchwork Wed Jun 14 01:12:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9785117 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 90F7F60384 for ; Wed, 14 Jun 2017 01:27:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 835D528419 for ; Wed, 14 Jun 2017 01:27:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7841728520; Wed, 14 Jun 2017 01:27:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 541DF28419 for ; Wed, 14 Jun 2017 01:27:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dKx4O-0007pv-Fy; Wed, 14 Jun 2017 01:26:04 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dKx4N-0007oN-70 for xen-devel@lists.xenproject.org; Wed, 14 Jun 2017 01:26:03 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id B8/7D-01992-AA090495; Wed, 14 Jun 2017 01:26:02 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRWlGSWpSXmKPExsVywNykWHflBId IgyNbjCy+b5nM5MDocfjDFZYAxijWzLyk/IoE1owbTzsYC2YYVPy91cnUwLhOtYuRi0NIYBqj xKbna1m7GDk5JAR4JY4smwFl+0n071nHClHUwCixctlldpAEm4C6xOOvPUwgtoiAksS9VZOZQ IqYBXYySaw7/Z0ZJCEs4CBx4tZPsCIWAVWJs5M3gU3lFfCUmPdvOzPEBjmJk8cmg8U5geLdr5 +B1QsJeEj8vDKVaQIj7wJGhlWMGsWpRWWpRbpGhnpJRZnpGSW5iZk5uoYGpnq5qcXFiempOYl JxXrJ+bmbGIEhUc/AwLiD8e5kv0OMkhxMSqK8S+wcIoX4kvJTKjMSizPii0pzUosPMcpwcChJ 8L7pA8oJFqWmp1akZeYAgxMmLcHBoyTCW9sGlOYtLkjMLc5Mh0idYlSUEuc9BdInAJLIKM2Da 4NFxCVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrzH+4Gm8GTmlcBNfwW0mAlo8fUrNiCLSx IRUlINjGf2HjCq4pmsZ2PEc0Zcu+5gZduu/a16bRMPPfjod/VBjMYqmy/xFTMmnBeoefHQmWn Fs7kxexX/zHRQWLFzsqtvp2bX9Y13/5T+Nv54YE7ZuYvfnpYI6DuveRAszrf09+vt5r5ZXgrR IqunxZm4bUu2eF1btkZi57u4BeHZAqtvbrZyNVtx7osSS3FGoqEWc1FxIgBbzyz2gwIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-16.tower-206.messagelabs.com!1497403511!87398197!17 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 50143 invoked from network); 14 Jun 2017 01:26:01 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-16.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 14 Jun 2017 01:26:01 -0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2017 18:26:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,340,1493708400"; d="scan'208";a="99173999" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.64]) by orsmga002.jf.intel.com with ESMTP; 13 Jun 2017 18:25:57 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Wed, 14 Jun 2017 09:12:49 +0800 Message-Id: <1497402776-22348-17-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497402776-22348-1-git-send-email-yi.y.sun@linux.intel.com> References: <1497402776-22348-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, he.chen@linux.intel.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v12 16/23] x86: L2 CAT: implement CPU init flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init flow for L2 CAT. Signed-off-by: Yi Sun --- v12: - move 'type[]' assignment into l2_cat_props declaration to make it be 'const'. (suggested by Jan Beulich) - add "L2 CAT" indicator in printk. (suggested by Jan Beulich) - restore mask(0) MSR to default value. (suggested by Jan Beulich) v11: - move l2 cat 'type[]' assignement into 'psr_cpu_init'. - remove COS MSR restore action in 'cpu_init_feature'. - set 'feat_init' to true after CPU init. - modify commit message. v10: - implement L2 CAT case in 'cat_init_feature'. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - introduce 'PSR_CBM_TYPE_L2'. v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- --- xen/arch/x86/psr.c | 34 ++++++++++++++++++++++++++++++++-- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 ++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 91b2122..60202b2 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -63,6 +63,7 @@ enum psr_feat_type { PSR_SOCKET_L3_CAT, PSR_SOCKET_L3_CDP, + PSR_SOCKET_L2_CAT, PSR_SOCKET_FEAT_NUM, PSR_SOCKET_FEAT_UNKNOWN, }; @@ -154,6 +155,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3_cat; static struct feat_node *feat_l3_cdp; +static struct feat_node *feat_l2_cat; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -279,10 +281,14 @@ static void cat_init_feature(const struct cpuid_leaf *regs, switch ( type ) { case PSR_SOCKET_L3_CAT: + case PSR_SOCKET_L2_CAT: /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ feat->cos_reg_val[0] = cat_default_val(feat->cbm_len); - wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len)); + if ( type == PSR_SOCKET_L3_CAT ) + wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len)); + else + wrmsrl(MSR_IA32_PSR_L2_MASK(0), cat_default_val(feat->cbm_len)); break; @@ -317,7 +323,8 @@ static void cat_init_feature(const struct cpuid_leaf *regs, return; printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", - ((type == PSR_SOCKET_L3_CDP) ? "CDP" : "L3 CAT"), + ((type == PSR_SOCKET_L3_CDP) ? "CDP" : + ((type == PSR_SOCKET_L3_CAT) ? "L3 CAT": "L2 CAT")), cpu_to_socket(smp_processor_id()), feat->cos_max, feat->cbm_len); } @@ -375,6 +382,12 @@ static const struct feat_props l3_cdp_props = { .write_msr = l3_cdp_write_msr, }; +/* L2 CAT props */ +static const struct feat_props l2_cat_props = { + .cos_num = 1, + .type[0] = PSR_CBM_TYPE_L2, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1357,6 +1370,10 @@ static int psr_cpu_prepare(void) (feat_l3_cdp = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2_cat == NULL && + (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1407,6 +1424,19 @@ static void psr_cpu_init(void) info->feat_init = true; } + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); + + feat = feat_l2_cat; + feat_l2_cat = NULL; + feat_props[PSR_SOCKET_L2_CAT] = &l2_cat_props; + cat_init_feature(®s, feat, info, PSR_SOCKET_L2_CAT); + + info->feat_init = true; + } + assoc_init: psr_assoc_init(); } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 771e750..6c49c6d 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -345,6 +345,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index 15b9a25..276fdd6 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -56,6 +57,7 @@ enum cbm_type { PSR_CBM_TYPE_L3, PSR_CBM_TYPE_L3_CODE, PSR_CBM_TYPE_L3_DATA, + PSR_CBM_TYPE_L2, }; extern struct psr_cmt *psr_cmt;