From patchwork Thu Jun 29 05:50:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9816523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C3F566020A for ; Thu, 29 Jun 2017 11:59:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C95D2521E for ; Thu, 29 Jun 2017 11:59:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0172028602; Thu, 29 Jun 2017 11:59:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5F6972521E for ; Thu, 29 Jun 2017 11:59:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dQY5W-0006X3-O3; Thu, 29 Jun 2017 11:58:22 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dQY5V-0006TB-FT for xen-devel@lists.xen.org; Thu, 29 Jun 2017 11:58:21 +0000 Received: from [85.158.139.211] by server-13.bemta-5.messagelabs.com id C5/52-01732-C5BE4595; Thu, 29 Jun 2017 11:58:20 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsXS1tbhqBvzOiT S4PE2PoslHxezODB6HN39mymAMYo1My8pvyKBNeP75QssBcs1K86f28LewHhFvouRi0NIYDqj xP1Fx5m7GDk5JAR4JY4sm8EKYQdIvOp7AmYLCbQzSvzfUgZiswmoS5xYPJERxBYRkJa49vkym M0ssI9R4s1zVRBbWCBYovH5MnYQm0VAVWLFmSVgNbwCrhLv921ihJivIDHl4XuwvZxA8YabW9 ggdrlIfOrZyTyBkXcBI8MqRo3i1KKy1CJdQyO9pKLM9IyS3MTMHF1DA1O93NTi4sT01JzEpGK 95PzcTYzAcGAAgh2MfbOcDzFKcjApifIaPg+JFOJLyk+pzEgszogvKs1JLT7EKMPBoSTB6/wK KCdYlJqeWpGWmQMMTJi0BAePkghvH0grb3FBYm5xZjpE6hSjopQ4bw1InwBIIqM0D64NFg2XG GWlhHkZgQ4R4ilILcrNLEGVf8UozsGoJMwrDzKFJzOvBG76K6DFTECLhWeALS5JREhJNTDmio v/5297cp7pzIs3nfuf7zKWDSvS/Xnznevermkzpl4+dcJciC3zyHuOln+d8hcjJyb2rH6hMTO jxWPRYe0Jf01sb2ol8c1Z9HAPi8iirrr6mU6bXbf1Ho7xsH1deWrm8aPdLh9EmdxfMN11mhOq lcXS+8A13fflw7iEsK+/y0V+nN06MeuREktxRqKhFnNRcSIANbLf1IECAAA= X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-6.tower-206.messagelabs.com!1498737497!100433764!1 X-Originating-IP: [134.134.136.65] X-SpamReason: No, hits=1.3 required=7.0 tests=BODY_RANDOM_LONG, DATE_IN_PAST_06_12 X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 35631 invoked from network); 29 Jun 2017 11:58:19 -0000 Received: from mga03.intel.com (HELO mga03.intel.com) (134.134.136.65) by server-6.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 29 Jun 2017 11:58:19 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jun 2017 04:58:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.40,280,1496127600"; d="scan'208"; a="1166110965" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.74]) by fmsmga001.fm.intel.com with ESMTP; 29 Jun 2017 04:58:11 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 29 Jun 2017 01:50:45 -0400 Message-Id: <1498715457-16565-14-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1498715457-16565-1-git-send-email-tianyu.lan@intel.com> References: <1498715457-16565-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, Chao Gao Subject: [Xen-devel] [PATCH 13/25] X86/vvtd: Set Interrupt Remapping Table Pointer through GCMD X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao Software sets this field to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address (IRTA_REG) register. This patch emulates this operation and adds some new fields in VVTD to track info (e.g. the table's gfn and max supported entries) of interrupt remapping table. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/drivers/passthrough/vtd/iommu.h | 9 ++++- xen/drivers/passthrough/vtd/vvtd.c | 73 +++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 55f3b6e..102b4f3 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -192,9 +192,16 @@ #define DMA_GSTS_WBFS (((u64)1) << 27) #define DMA_GSTS_QIES (((u64)1) <<26) #define DMA_GSTS_IRES (((u64)1) <<25) -#define DMA_GSTS_SIRTPS (((u64)1) << 24) +#define DMA_GSTS_SIRTPS_BIT 24 +#define DMA_GSTS_SIRTPS (((u64)1) << DMA_GSTS_SIRTPS_BIT) #define DMA_GSTS_CFIS (((u64)1) <<23) +/* IRTA_REG */ +#define DMA_IRTA_ADDR(val) (val & ~0xfffULL) +#define DMA_IRTA_EIME(val) (!!(val & (1 << 11))) +#define DMA_IRTA_S(val) (val & 0xf) +#define DMA_IRTA_SIZE(val) (1UL << (DMA_IRTA_S(val) + 1)) + /* PMEN_REG */ #define DMA_PMEN_EPM (((u32)1) << 31) #define DMA_PMEN_PRS (((u32)1) << 0) diff --git a/xen/drivers/passthrough/vtd/vvtd.c b/xen/drivers/passthrough/vtd/vvtd.c index 0945970..80c7e96 100644 --- a/xen/drivers/passthrough/vtd/vvtd.c +++ b/xen/drivers/passthrough/vtd/vvtd.c @@ -46,6 +46,13 @@ struct vvtd { uint64_t length; /* Point back to the owner domain */ struct domain *domain; + /* Is in Extended Interrupt Mode? */ + bool eim; + /* Max remapping entries in IRT */ + int irt_max_entry; + /* Interrupt remapping table base gfn */ + uint64_t irt; + struct hvm_hw_vvtd_regs *regs; struct page_info *regs_page; }; @@ -82,6 +89,11 @@ static inline struct vvtd *vcpu_vvtd(struct vcpu *v) return domain_vvtd(v->domain); } +static inline void __vvtd_set_bit(struct vvtd *vvtd, uint32_t reg, int nr) +{ + return __set_bit(nr, (uint32_t *)&vvtd->regs->data[reg]); +} + static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg, uint32_t value) { @@ -108,6 +120,44 @@ static inline uint8_t vvtd_get_reg_byte(struct vvtd *vtd, uint32_t reg) vvtd_set_reg(vvtd, (reg) + 4, (val) >> 32); \ } while(0) +static int vvtd_handle_gcmd_sirtp(struct vvtd *vvtd, uint32_t val) +{ + uint64_t irta; + + if ( !(val & DMA_GCMD_SIRTP) ) + return X86EMUL_OKAY; + + vvtd_get_reg_quad(vvtd, DMAR_IRTA_REG, irta); + vvtd->irt = DMA_IRTA_ADDR(irta) >> PAGE_SHIFT; + vvtd->irt_max_entry = DMA_IRTA_SIZE(irta); + vvtd->eim = DMA_IRTA_EIME(irta); + VVTD_DEBUG(VVTD_DBG_RW, "Update IR info (addr=%lx eim=%d size=%d).", + vvtd->irt, vvtd->eim, vvtd->irt_max_entry); + __vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_SIRTPS_BIT); + + return X86EMUL_OKAY; +} + +static int vvtd_write_gcmd(struct vvtd *vvtd, uint32_t val) +{ + uint32_t orig = vvtd_get_reg(vvtd, DMAR_GSTS_REG); + uint32_t changed; + + orig = orig & 0x96ffffff; /* reset the one-shot bits */ + changed = orig ^ val; + + if ( !changed ) + return X86EMUL_OKAY; + if ( (changed & (changed - 1)) ) + VVTD_DEBUG(VVTD_DBG_RW, "Guest attempts to update multiple fields " + "of GCMD_REG in one write transation."); + + if ( changed & DMA_GCMD_SIRTP ) + vvtd_handle_gcmd_sirtp(vvtd, val); + + return X86EMUL_OKAY; +} + static int vvtd_range(struct vcpu *v, unsigned long addr) { struct vvtd *vvtd = vcpu_vvtd(v); @@ -165,12 +215,18 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, { switch ( offset_aligned ) { + case DMAR_GCMD_REG: + ret = vvtd_write_gcmd(vvtd, val); + break; + case DMAR_IEDATA_REG: case DMAR_IEADDR_REG: case DMAR_IEUADDR_REG: case DMAR_FEDATA_REG: case DMAR_FEADDR_REG: case DMAR_FEUADDR_REG: + case DMAR_IRTA_REG: + case DMAR_IRTA_REG_HI: vvtd_set_reg(vvtd, offset_aligned, val); ret = X86EMUL_OKAY; break; @@ -179,6 +235,20 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, break; } } + else /* len == 8 */ + { + switch ( offset_aligned ) + { + case DMAR_IRTA_REG: + vvtd_set_reg_quad(vvtd, DMAR_IRTA_REG, val); + ret = X86EMUL_OKAY; + break; + + default: + ret = X86EMUL_UNHANDLEABLE; + break; + } + } return ret; } @@ -236,6 +306,9 @@ static int vvtd_create(struct domain *d, struct viommu *viommu) vvtd->length = viommu->length; vvtd->domain = d; vvtd->status = 0; + vvtd->eim = 0; + vvtd->irt = 0; + vvtd->irt_max_entry = 0; register_mmio_handler(d, &vvtd_mmio_ops); return 0;