@@ -190,7 +190,8 @@
#define DMA_GSTS_FLS (((u64)1) << 29)
#define DMA_GSTS_AFLS (((u64)1) << 28)
#define DMA_GSTS_WBFS (((u64)1) << 27)
-#define DMA_GSTS_QIES (((u64)1) <<26)
+#define DMA_GSTS_QIES_BIT 26
+#define DMA_GSTS_QIES (((u64)1) << DMA_GSTS_QIES_BIT)
#define DMA_GSTS_IRES (((u64)1) <<25)
#define DMA_GSTS_SIRTPS_BIT 24
#define DMA_GSTS_SIRTPS (((u64)1) << DMA_GSTS_SIRTPS_BIT)
@@ -102,6 +102,11 @@ static inline void __vvtd_set_bit(struct vvtd *vvtd, uint32_t reg, int nr)
return __set_bit(nr, (uint32_t *)&vvtd->regs->data[reg]);
}
+static inline void __vvtd_clear_bit(struct vvtd *vvtd, uint32_t reg, int nr)
+{
+ return __clear_bit(nr, (uint32_t *)&vvtd->regs->data[reg]);
+}
+
static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg,
uint32_t value)
{
@@ -262,6 +267,21 @@ static int vvtd_record_fault(struct vvtd *vvtd,
return 0;
}
+static int vvtd_handle_gcmd_qie(struct vvtd *vvtd, uint32_t val)
+{
+ VVTD_DEBUG(VVTD_DBG_RW, "%sable Queue Invalidation.",
+ (val & DMA_GCMD_QIE) ? "En" : "Dis");
+
+ if ( val & DMA_GCMD_QIE )
+ __vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_QIES_BIT);
+ else
+ {
+ vvtd_set_reg_quad(vvtd, DMAR_IQH_REG, 0ULL);
+ __vvtd_clear_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_QIES_BIT);
+ }
+ return X86EMUL_OKAY;
+}
+
static int vvtd_handle_gcmd_sirtp(struct vvtd *vvtd, uint32_t val)
{
uint64_t irta;
@@ -296,6 +316,8 @@ static int vvtd_write_gcmd(struct vvtd *vvtd, uint32_t val)
if ( changed & DMA_GCMD_SIRTP )
vvtd_handle_gcmd_sirtp(vvtd, val);
+ if ( changed & DMA_GCMD_QIE )
+ vvtd_handle_gcmd_qie(vvtd, val);
return X86EMUL_OKAY;
}