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[85.223.141.74]) by smtp.gmail.com with ESMTPSA id q23sm3610873lfq.92.2017.07.27.07.55.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 27 Jul 2017 07:55:11 -0700 (PDT) From: Andrii Anisov To: xen-devel@lists.xen.org Date: Thu, 27 Jul 2017 17:55:10 +0300 Message-Id: <1501167310-32282-1-git-send-email-andrii.anisov@gmail.com> X-Mailer: git-send-email 2.7.4 Cc: julien.grall@arm.com, sstabellini@kernel.org, Andrii Anisov Subject: [Xen-devel] [PATCH] xen/arm: Fix comments coding style in assembler files X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Andrii Anisov Signed-off-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm32/debug-8250.inc | 12 +++-- xen/arch/arm/arm32/debug-exynos4210.inc | 12 +++-- xen/arch/arm/arm32/debug-pl011.inc | 18 +++++--- xen/arch/arm/arm32/debug-scif.inc | 6 ++- xen/arch/arm/arm32/debug.S | 6 ++- xen/arch/arm/arm32/head.S | 81 ++++++++++++++++++++++----------- xen/arch/arm/arm64/debug-8250.inc | 12 +++-- xen/arch/arm/arm64/debug-cadence.inc | 12 +++-- xen/arch/arm/arm64/debug-pl011.inc | 18 +++++--- xen/arch/arm/arm64/debug.S | 6 ++- xen/arch/arm/arm64/entry.S | 50 ++++++++++---------- 11 files changed, 147 insertions(+), 86 deletions(-) diff --git a/xen/arch/arm/arm32/debug-8250.inc b/xen/arch/arm/arm32/debug-8250.inc index 757ffd8..0759a27 100644 --- a/xen/arch/arm/arm32/debug-8250.inc +++ b/xen/arch/arm/arm32/debug-8250.inc @@ -16,9 +16,11 @@ #include -/* 8250 UART wait UART to be ready to transmit +/* + * 8250 UART wait UART to be ready to transmit * rb: register which contains the UART base address - * rc: scratch register */ + * rc: scratch register + */ .macro early_uart_ready rb rc 1: ldr \rc, [\rb, #(UART_LSR << EARLY_UART_REG_SHIFT)] /* Read LSR */ @@ -26,9 +28,11 @@ beq 1b /* Wait for the UART to be ready */ .endm -/* 8250 UART transmit character +/* + * 8250 UART transmit character * rb: register which contains the UART base address - * rt: register which contains the character to transmit */ + * rt: register which contains the character to transmit + */ .macro early_uart_transmit rb rt str \rt, [\rb, #UART_THR] /* Write Transmit buffer */ .endm diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc index 752942d..4e80a21 100644 --- a/xen/arch/arm/arm32/debug-exynos4210.inc +++ b/xen/arch/arm/arm32/debug-exynos4210.inc @@ -18,9 +18,11 @@ #include -/* Exynos 5 UART wait UART to be ready to transmit +/* + * Exynos 5 UART wait UART to be ready to transmit * rb: register which contains the UART base address - * rc: scratch register */ + * rc: scratch register + */ .macro early_uart_ready rb rc 1: ldr \rc, [\rb, #UTRSTAT] /* <- UTRSTAT (Flag register) */ @@ -28,9 +30,11 @@ beq 1b /* Wait for the UART to be ready */ .endm -/* Exynos 5 UART transmit character +/* + * Exynos 5 UART transmit character * rb: register which contains the UART base address - * rt: register which contains the character to transmit */ + * rt: register which contains the character to transmit + */ .macro early_uart_transmit rb rt str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */ .endm diff --git a/xen/arch/arm/arm32/debug-pl011.inc b/xen/arch/arm/arm32/debug-pl011.inc index 6a64dbf..ec462ea 100644 --- a/xen/arch/arm/arm32/debug-pl011.inc +++ b/xen/arch/arm/arm32/debug-pl011.inc @@ -18,10 +18,12 @@ #include -/* PL011 UART initialization +/* + * PL011 UART initialization * rb: register which contains the UART base address * rc: scratch register 1 - * rd: scratch register 2 (unused here) */ + * rd: scratch register 2 (unused here) + */ .macro early_uart_init rb, rc, rd mov \rc, #(7372800 / EARLY_PRINTK_BAUD % 16) str \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ @@ -33,9 +35,11 @@ str \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ .endm -/* PL011 UART wait UART to be ready to transmit +/* + * PL011 UART wait UART to be ready to transmit * rb: register which contains the UART base address - * rc: scratch register */ + * rc: scratch register + */ .macro early_uart_ready rb, rc 1: ldr \rc, [\rb, #FR] /* <- UARTFR (Flag register) */ @@ -43,9 +47,11 @@ bne 1b /* Wait for the UART to be ready */ .endm -/* PL011 UART transmit character +/* + * PL011 UART transmit character * rb: register which contains the UART base address - * rt: register which contains the character to transmit */ + * rt: register which contains the character to transmit + */ .macro early_uart_transmit rb, rt str \rt, [\rb, #DR] /* -> UARTDR (Data Register) */ .endm diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-scif.inc index ce85752..143f05d 100644 --- a/xen/arch/arm/arm32/debug-scif.inc +++ b/xen/arch/arm/arm32/debug-scif.inc @@ -19,7 +19,8 @@ #include -/* SCIF UART wait UART to be ready to transmit +/* + * SCIF UART wait UART to be ready to transmit * rb: register which contains the UART base address * rc: scratch register */ @@ -30,7 +31,8 @@ beq 1b /* Wait for the UART to be ready */ .endm -/* SCIF UART transmit character +/* + * SCIF UART transmit character * rb: register which contains the UART base address * rt: register which contains the character to transmit */ diff --git a/xen/arch/arm/arm32/debug.S b/xen/arch/arm/arm32/debug.S index 1538090..1829b29 100644 --- a/xen/arch/arm/arm32/debug.S +++ b/xen/arch/arm/arm32/debug.S @@ -23,8 +23,10 @@ #include EARLY_PRINTK_INC #endif -/* Print a character on the UART - this function is called by C - * r0: character to print */ +/* + * Print a character on the UART - this function is called by C + * r0: character to print + */ GLOBAL(early_putch) ldr r1, =EARLY_UART_VIRTUAL_ADDRESS /* r1 := VA UART base address */ early_uart_ready r1, r2 diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4090f4a..43374e7 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -71,12 +71,15 @@ .arm - /* This must be the very first address in the loaded image. + /* + * This must be the very first address in the loaded image. * It should be linked at XEN_VIRT_START, and loaded at any * 4K-aligned address. All of text+data+bss must fit in 2MB, - * or the initial pagetable code below will need adjustment. */ + * or the initial pagetable code below will need adjustment. + */ GLOBAL(start) - /* zImage magic header, see: + /* + * zImage magic header, see: * http://www.simtec.co.uk/products/SWLINUX/files/booting_article.html#d0e309 */ .rept 8 @@ -222,33 +225,40 @@ cpu_init_done: mcr CP32(r0, HMAIR0) mcr CP32(r1, HMAIR1) - /* Set up the HTCR: + /* + * Set up the HTCR: * PT walks use Inner-Shareable accesses, * PT walks are write-back, write-allocate in both cache levels, - * Full 32-bit address space goes through this table. */ + * Full 32-bit address space goes through this table. + */ ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* Set up the HSCTLR: + /* + * Set up the HSCTLR: * Exceptions in LE ARM, * Low-latency IRQs disabled, * Write-implies-XN disabled (for now), * D-cache disabled (for now), * I-cache enabled, * Alignment checking enabled, - * MMU translation disabled (for now). */ + * MMU translation disabled (for now). + */ ldr r0, =(HSCTLR_BASE|SCTLR_A) mcr CP32(r0, HSCTLR) - /* Rebuild the boot pagetable's first-level entries. The structure + /* + * Rebuild the boot pagetable's first-level entries. The structure * is described in mm.c. * * After the CPU enables paging it will add the fixmap mapping * to these page tables, however this may clash with the 1:1 * mapping. So each CPU must rebuild the page tables here with - * the 1:1 in place. */ + * the 1:1 in place. + */ - /* If Xen is loaded at exactly XEN_VIRT_START then we don't + /* + * If Xen is loaded at exactly XEN_VIRT_START then we don't * need an additional 1:1 mapping, the virtual mapping will * suffice. */ @@ -331,8 +341,10 @@ cpu_init_done: cmp r1, #(LPAE_ENTRIES<<3) /* 512*8-byte entries per page */ blo 1b - /* Defer fixmap and dtb mapping until after paging enabled, to - * avoid them clashing with the 1:1 mapping. */ + /* + * Defer fixmap and dtb mapping until after paging enabled, to + * avoid them clashing with the 1:1 mapping. + */ /* boot pagetable setup complete */ @@ -357,12 +369,16 @@ virtphys_clash: mov pc, r1 /* Get a proper vaddr into PC */ paging: - /* Now we can install the fixmap and dtb mappings, since we - * don't need the 1:1 map any more */ + /* + * Now we can install the fixmap and dtb mappings, since we + * don't need the 1:1 map any more + */ dsb #if defined(CONFIG_EARLY_PRINTK) /* Fixmap is only used by early printk */ - /* Non-boot CPUs don't need to rebuild the fixmap itself, just - * the mapping from boot_second to xen_fixmap */ + /* + * Non-boot CPUs don't need to rebuild the fixmap itself, just + * the mapping from boot_second to xen_fixmap + */ teq r12, #0 bne 1f @@ -408,8 +424,10 @@ paging: teq r12, #0 beq launch - /* Non-boot CPUs need to move on to the proper pagetables, which were - * setup in init_secondary_pagetables. */ + /* + * Non-boot CPUs need to move on to the proper pagetables, which were + * setup in init_secondary_pagetables. + */ ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */ ldrd r4, r5, [r4] /* Actual value */ @@ -443,7 +461,8 @@ fail: PRINT("- Boot failed -\r\n") GLOBAL(_end_boot) -/* Copy Xen to new location and switch TTBR +/* + * Copy Xen to new location and switch TTBR * r1:r0 ttbr * r2 source address * r3 destination address @@ -452,7 +471,8 @@ GLOBAL(_end_boot) * Source and destination must be word aligned, length is rounded up * to a 16 byte boundary. * - * MUST BE VERY CAREFUL when saving things to RAM over the copy */ + * MUST BE VERY CAREFUL when saving things to RAM over the copy + */ ENTRY(relocate_xen) push {r4,r5,r6,r7,r8,r9,r10,r11} @@ -521,9 +541,11 @@ ENTRY(relocate_xen) mov pc, lr #ifdef CONFIG_EARLY_PRINTK -/* Bring up the UART. +/* + * Bring up the UART. * r11: Early UART base address - * Clobbers r0-r2 */ + * Clobbers r0-r2 + */ init_uart: #ifdef EARLY_PRINTK_INIT_UART early_uart_init r11, r1, r2 @@ -533,10 +555,12 @@ init_uart: 1: .asciz "- UART enabled -\r\n" .align 4 -/* Print early debug messages. +/* + * Print early debug messages. * r0: Nul-terminated string to print. * r11: Early UART base address - * Clobbers r0-r1 */ + * Clobbers r0-r1 + */ puts: early_uart_ready r11, r1 ldrb r1, [r0], #1 /* Load next char */ @@ -545,10 +569,12 @@ puts: early_uart_transmit r11, r1 b puts -/* Print a 32-bit number in hex. Specific to the PL011 UART. +/* + * Print a 32-bit number in hex. Specific to the PL011 UART. * r0: Number to print. * r11: Early UART base address - * Clobbers r0-r3 */ + * Clobbers r0-r3 + */ putn: adr r1, hex mov r3, #8 @@ -582,7 +608,8 @@ ENTRY(lookup_processor_type) mov r0, r1 ldmfd sp!, {r4, r10, pc} -/* Read processor ID register (CP#15, CR0), and Look up in the linker-built +/* + * Read processor ID register (CP#15, CR0), and Look up in the linker-built * supported processor list. Note that we can't use the absolute addresses for * the __proc_info lists since we aren't running with the MMU on (and therefore, * we are not in correct address space). We have to calculate the offset. diff --git a/xen/arch/arm/arm64/debug-8250.inc b/xen/arch/arm/arm64/debug-8250.inc index 158549a..53d6828 100644 --- a/xen/arch/arm/arm64/debug-8250.inc +++ b/xen/arch/arm/arm64/debug-8250.inc @@ -18,9 +18,11 @@ #include -/* UART wait UART to be ready to transmit +/* + * UART wait UART to be ready to transmit * xb: register which contains the UART base address - * c: scratch register */ + * c: scratch register + */ .macro early_uart_ready xb c 1: ldrb w\c, [\xb, #UART_LSR << EARLY_UART_REG_SHIFT] @@ -29,9 +31,11 @@ b.ne 1b .endm -/* UART transmit character +/* + * UART transmit character * xb: register which contains the UART base address - * wt: register which contains the character to transmit */ + * wt: register which contains the character to transmit + */ .macro early_uart_transmit xb wt /* UART_THR transmit holding */ strb \wt, [\xb, #UART_THR << EARLY_UART_REG_SHIFT] diff --git a/xen/arch/arm/arm64/debug-cadence.inc b/xen/arch/arm/arm64/debug-cadence.inc index 84dee4c..7df0abe 100644 --- a/xen/arch/arm/arm64/debug-cadence.inc +++ b/xen/arch/arm/arm64/debug-cadence.inc @@ -20,9 +20,11 @@ #include #include -/* Cadence UART wait UART to be ready to transmit +/* + * Cadence UART wait UART to be ready to transmit * xb: register which contains the UART base address - * c: scratch register number */ + * c: scratch register number + */ .macro early_uart_ready xb, c 1: ldrh w\c, [\xb, #R_UART_SR] @@ -30,9 +32,11 @@ b.ne 1b .endm -/* Cadence UART transmit character +/* + * Cadence UART transmit character * xb: register which contains the UART base address - * wt: register which contains the character to transmit */ + * wt: register which contains the character to transmit + */ .macro early_uart_transmit xb, wt strb \wt, [\xb, #R_UART_TX] .endm diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-pl011.inc index b416235..569c3df 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -18,9 +18,11 @@ #include -/* PL011 UART initialization +/* + * PL011 UART initialization * xb: register which containts the UART base address - * c: scratch register number */ + * c: scratch register number + */ .macro early_uart_init xb, c mov x\c, #(7372800 / EARLY_PRINTK_BAUD % 16) strh w\c, [\xb, #0x28] /* -> UARTFBRD (Baud divisor fraction) */ @@ -32,9 +34,11 @@ str w\c, [\xb, #0x30] /* -> UARTCR (Control Register) */ .endm -/* PL011 UART wait UART to be ready to transmit +/* + * PL011 UART wait UART to be ready to transmit * xb: register which contains the UART base address - * c: scratch register number */ + * c: scratch register number + */ .macro early_uart_ready xb, c 1: ldrh w\c, [\xb, #0x18] /* <- UARTFR (Flag register) */ @@ -42,9 +46,11 @@ b.ne 1b /* Wait for the UART to be ready */ .endm -/* PL011 UART transmit character +/* + * PL011 UART transmit character * xb: register which contains the UART base address - * wt: register which contains the character to transmit */ + * wt: register which contains the character to transmit + */ .macro early_uart_transmit xb, wt strb \wt, [\xb] /* -> UARTDR (Data Register) */ .endm diff --git a/xen/arch/arm/arm64/debug.S b/xen/arch/arm/arm64/debug.S index 87ee8dc..b7f53ac 100644 --- a/xen/arch/arm/arm64/debug.S +++ b/xen/arch/arm/arm64/debug.S @@ -23,8 +23,10 @@ #include EARLY_PRINTK_INC #endif -/* Print a character on the UART - this function is called by C - * x0: character to print */ +/* + * Print a character on the UART - this function is called by C + * x0: character to print + */ GLOBAL(early_putch) ldr x15, =EARLY_UART_VIRTUAL_ADDRESS early_uart_ready x15, 1 diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 06afc8a..6d99e46 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -6,7 +6,7 @@ /* * Register aliases. */ -lr .req x30 // link register +lr .req x30 /* link register */ /* * Stack pushing/popping (register pairs only). Equivalent to store decrement @@ -293,8 +293,8 @@ ENTRY(return_to_new_vcpu64) return_from_trap: msr daifset, #2 /* Mask interrupts */ - ldr x21, [sp, #UREGS_PC] // load ELR - ldr w22, [sp, #UREGS_CPSR] // load SPSR + ldr x21, [sp, #UREGS_PC] /* load ELR */ + ldr w22, [sp, #UREGS_CPSR] /* load SPSR */ pop x0, x1 pop x2, x3 @@ -302,7 +302,7 @@ return_from_trap: pop x6, x7 pop x8, x9 - msr elr_el2, x21 // set up the return data + msr elr_el2, x21 /* set up the return data */ msr spsr_el2, x22 pop x10, x11 @@ -388,25 +388,25 @@ abort_guest_exit_end: .align 11 ENTRY(hyp_traps_vector) - ventry hyp_sync_invalid // Synchronous EL2t - ventry hyp_irq_invalid // IRQ EL2t - ventry hyp_fiq_invalid // FIQ EL2t - ventry hyp_error_invalid // Error EL2t - - ventry hyp_sync // Synchronous EL2h - ventry hyp_irq // IRQ EL2h - ventry hyp_fiq_invalid // FIQ EL2h - ventry hyp_error // Error EL2h - - ventry guest_sync // Synchronous 64-bit EL0/EL1 - ventry guest_irq // IRQ 64-bit EL0/EL1 - ventry guest_fiq_invalid // FIQ 64-bit EL0/EL1 - ventry guest_error // Error 64-bit EL0/EL1 - - ventry guest_sync_compat // Synchronous 32-bit EL0/EL1 - ventry guest_irq_compat // IRQ 32-bit EL0/EL1 - ventry guest_fiq_invalid_compat // FIQ 32-bit EL0/EL1 - ventry guest_error_compat // Error 32-bit EL0/EL1 + ventry hyp_sync_invalid /* Synchronous EL2t */ + ventry hyp_irq_invalid /* IRQ EL2t */ + ventry hyp_fiq_invalid /* FIQ EL2t */ + ventry hyp_error_invalid /* Error EL2t */ + + ventry hyp_sync /* Synchronous EL2h */ + ventry hyp_irq /* IRQ EL2h */ + ventry hyp_fiq_invalid /* FIQ EL2h */ + ventry hyp_error /* Error EL2h */ + + ventry guest_sync /* Synchronous 64-bit EL0/EL1 */ + ventry guest_irq /* IRQ 64-bit EL0/EL1 */ + ventry guest_fiq_invalid /* FIQ 64-bit EL0/EL1 */ + ventry guest_error /* Error 64-bit EL0/EL1 */ + + ventry guest_sync_compat /* Synchronous 32-bit EL0/EL1 */ + ventry guest_irq_compat /* IRQ 32-bit EL0/EL1 */ + ventry guest_fiq_invalid_compat /* FIQ 32-bit EL0/EL1 */ + ventry guest_error_compat /* Error 32-bit EL0/EL1 */ /* * struct vcpu *__context_switch(struct vcpu *prev, struct vcpu *next) @@ -419,7 +419,7 @@ ENTRY(hyp_traps_vector) ENTRY(__context_switch) add x8, x0, #VCPU_arch_saved_context mov x9, sp - stp x19, x20, [x8], #16 // store callee-saved registers + stp x19, x20, [x8], #16 /* store callee-saved registers */ stp x21, x22, [x8], #16 stp x23, x24, [x8], #16 stp x25, x26, [x8], #16 @@ -428,7 +428,7 @@ ENTRY(__context_switch) str lr, [x8] add x8, x1, #VCPU_arch_saved_context - ldp x19, x20, [x8], #16 // restore callee-saved registers + ldp x19, x20, [x8], #16 /* restore callee-saved registers */ ldp x21, x22, [x8], #16 ldp x23, x24, [x8], #16 ldp x25, x26, [x8], #16