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Wed, 09 Aug 2017 22:44:55 +0300 From: Volodymyr Babchuk To: xen-devel@lists.xen.org Date: Wed, 9 Aug 2017 22:44:27 +0300 Message-Id: <1502307870-11317-2-git-send-email-volodymyr_babchuk@epam.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502307870-11317-1-git-send-email-volodymyr_babchuk@epam.com> References: <1502307870-11317-1-git-send-email-volodymyr_babchuk@epam.com> MIME-Version: 1.0 X-Originating-IP: [85.223.209.53] X-ClientProxiedBy: HE1PR0202CA0024.eurprd02.prod.outlook.com (2603:10a6:3:8c::34) To VI1PR0301MB2144.eurprd03.prod.outlook.com (2603:10a6:800:26::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a2b0b622-beec-4970-f827-08d4df5f1fd8 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); 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ARM refence manual denotes this part of ISS as RES0 when it describes encoding for conditional exceptions (ARM DDI 0487A.k pages D7-1939 - D7-1949). Signed-off-by: Volodymyr Babchuk --- - Added reference to ARM archtecture manual in the commit message. --- xen/include/asm-arm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 855ded1..f640d54 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -434,7 +434,7 @@ union hsr { /* Common to all conditional exception classes (0x0N, except 0x00). */ struct hsr_cond { - unsigned long iss:20; /* Instruction Specific Syndrome */ + unsigned long res0:20; /* Reserved */ unsigned long cc:4; /* Condition Code */ unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */