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Wed, 09 Aug 2017 22:45:02 +0300 From: Volodymyr Babchuk To: xen-devel@lists.xen.org Date: Wed, 9 Aug 2017 22:44:28 +0300 Message-Id: <1502307870-11317-3-git-send-email-volodymyr_babchuk@epam.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502307870-11317-1-git-send-email-volodymyr_babchuk@epam.com> References: <1502307870-11317-1-git-send-email-volodymyr_babchuk@epam.com> MIME-Version: 1.0 X-Originating-IP: [85.223.209.53] X-ClientProxiedBy: VI1P18901CA0016.EURP189.PROD.OUTLOOK.COM (2603:10a6:801::26) To HE1PR0301MB2139.eurprd03.prod.outlook.com (2603:10a6:3:21::16) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 807c7347-72f0-4700-1609-08d4df5f2447 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); 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(ARM DDI 0487A.k page D7-1949) This is instruction specific field, so better to add new structure to union hsr. This structure describes ISS encoding for an exception from SMC instruction execution in AArch32 state. But we define this struct for both ARMv7 and ARMv8. The reason is described in comment to the structure: "Nevertheless, we define this encoding for both ARMv7 and ARMv8, because check_conditional_inst() should properly handle SMC instruction in all modes: ARMv7, aarch32 and aarch64." Signed-off-by: Volodymyr Babchuk --- - Created new stucture for HSR_EC_SMC32 instead of extending fields in hsr.cond. - Added references to ARM manual. - Wrote comment with rationale. --- xen/include/asm-arm/processor.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index f640d54..af4a0f7 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -488,6 +488,25 @@ union hsr { unsigned long ec:6; /* Exception Class */ } cp; /* HSR_EC_CP */ + /* + * This encoding is valid only for ARMv8 (ARM DDI 0487A.k pages D7-1949 and + * G6-4405). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP + * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements + * this field as Read-As-Zero. + * + * Nevertheless, we define this encoding for both ARMv7 and ARMv8, because + * check_conditional_inst() should properly handle SMC instruction in all + * modes: ARMv7, aarch32 and aarch64. + */ + struct hsr_smc32 { + unsigned long res0:19; /* Reserved */ + unsigned long ccknownpass:1; /* Instruction passed conditional check */ + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } smc32; /* HSR_EC_SMC32 */ + #ifdef CONFIG_ARM_64 struct hsr_sysreg { unsigned long read:1; /* Direction */