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Thu, 31 Aug 2017 23:10:47 +0300 From: Volodymyr Babchuk To: xen-devel@lists.xen.org Date: Thu, 31 Aug 2017 23:09:31 +0300 Message-Id: <1504210172-27234-10-git-send-email-volodymyr_babchuk@epam.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504210172-27234-1-git-send-email-volodymyr_babchuk@epam.com> References: <1504210172-27234-1-git-send-email-volodymyr_babchuk@epam.com> MIME-Version: 1.0 X-Originating-IP: [85.223.209.51] X-ClientProxiedBy: HE1PR09CA0079.eurprd09.prod.outlook.com (2603:10a6:7:3d::23) To DB6PR0301MB2136.eurprd03.prod.outlook.com (2603:10a6:4:46::18) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1da0ac1c-fe8a-4513-0d05-08d4f0ac61b1 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); 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Iglesias" , Julien Grall , Stefano Stabellini , Volodymyr Babchuk Subject: [Xen-devel] [PATCH v5 09/10] arm: vsmc: remove 64 bit mode check in PSCI handler X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP PSCI handling code had helper routine that checked calling convention. It does not needed anymore, because: - Generic handler checks that 64 bit calls can be made only by 64 bit guests. - SMCCC requires that 64-bit handler should support both 32 and 64 bit calls even if they originate from 64 bit caller. This patch removes that extra check. Signed-off-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- xen/arch/arm/vsmc.c | 62 ++++++++++++++++++++++------------------------------- 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 5421bd2..e778173 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -111,12 +111,6 @@ static bool handle_existing_apis(struct cpu_user_regs *regs) } } -/* helper function for checking arm mode 32/64 bit */ -static inline int psci_mode_check(struct domain *d, register_t fid) -{ - return is_64bit_domain(d) || !smccc_is_conv_64(fid); -} - /* PSCI 0.2 interface and other Standard Secure Calls */ static bool handle_sssc(struct cpu_user_regs *regs) { @@ -141,8 +135,7 @@ static bool handle_sssc(struct cpu_user_regs *regs) case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: perfc_incr(vpsci_migrate_info_up_cpu); - if ( psci_mode_check(current->domain, fid) ) - PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_up_cpu()); + PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_up_cpu()); return true; case PSCI_0_2_FN_SYSTEM_OFF: @@ -158,48 +151,45 @@ static bool handle_sssc(struct cpu_user_regs *regs) return true; case PSCI_0_2_FN_CPU_ON: - perfc_incr(vpsci_cpu_on); - if ( psci_mode_check(current->domain, fid) ) - { - register_t vcpuid = PSCI_ARG(regs, 1); - register_t epoint = PSCI_ARG(regs, 2); - register_t cid = PSCI_ARG(regs, 3); + { + register_t vcpuid = PSCI_ARG(regs, 1); + register_t epoint = PSCI_ARG(regs, 2); + register_t cid = PSCI_ARG(regs, 3); - PSCI_SET_RESULT(regs, do_psci_0_2_cpu_on(vcpuid, epoint, cid)); - } + perfc_incr(vpsci_cpu_on); + PSCI_SET_RESULT(regs, do_psci_0_2_cpu_on(vcpuid, epoint, cid)); return true; + } case PSCI_0_2_FN_CPU_SUSPEND: - perfc_incr(vpsci_cpu_suspend); - if ( psci_mode_check(current->domain, fid) ) - { - uint32_t pstate = PSCI_ARG32(regs, 1); - register_t epoint = PSCI_ARG(regs, 2); - register_t cid = PSCI_ARG(regs, 3); + { + uint32_t pstate = PSCI_ARG32(regs, 1); + register_t epoint = PSCI_ARG(regs, 2); + register_t cid = PSCI_ARG(regs, 3); - PSCI_SET_RESULT(regs, do_psci_0_2_cpu_suspend(pstate, epoint, cid)); - } + perfc_incr(vpsci_cpu_suspend); + PSCI_SET_RESULT(regs, do_psci_0_2_cpu_suspend(pstate, epoint, cid)); return true; + } case PSCI_0_2_FN_AFFINITY_INFO: + { + register_t taff = PSCI_ARG(regs, 1); + uint32_t laff = PSCI_ARG32(regs, 2); + perfc_incr(vpsci_cpu_affinity_info); - if ( psci_mode_check(current->domain, fid) ) - { - register_t taff = PSCI_ARG(regs, 1); - uint32_t laff = PSCI_ARG32(regs, 2); - PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); - } + PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; + } case PSCI_0_2_FN_MIGRATE: - perfc_incr(vpsci_cpu_migrate); - if ( psci_mode_check(current->domain, fid) ) - { - uint32_t tcpu = PSCI_ARG32(regs, 1); + { + uint32_t tcpu = PSCI_ARG32(regs, 1); - PSCI_SET_RESULT(regs, do_psci_0_2_migrate(tcpu)); - } + perfc_incr(vpsci_cpu_migrate); + PSCI_SET_RESULT(regs, do_psci_0_2_migrate(tcpu)); return true; + } case ARM_SMCCC_FUNC_CALL_COUNT: set_user_reg(regs, 0, SSSC_SMCCC_FUNCTION_COUNT);