From patchwork Tue Sep 5 09:32:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9938331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EADDC601EB for ; Tue, 5 Sep 2017 09:53:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD08828902 for ; Tue, 5 Sep 2017 09:53:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D21BF2890B; Tue, 5 Sep 2017 09:53:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0BC4C28908 for ; Tue, 5 Sep 2017 09:53:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dpAVr-00071p-AO; Tue, 05 Sep 2017 09:51:19 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dpAVp-000718-Kh for xen-devel@lists.xenproject.org; Tue, 05 Sep 2017 09:51:17 +0000 Received: from [193.109.254.147] by server-3.bemta-6.messagelabs.com id 3F/85-03093-4937EA95; Tue, 05 Sep 2017 09:51:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRWlGSWpSXmKPExsXS1taRoju5eF2 kwf0pshbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bKxsOsBbvSK2bNe8HawLjZt4uRk0NIoFLi 4aTrjCC2hACvxJFlM1ghbH+Js8+/AsW5gGoaGCW+T+1iAkmwCahLPP7aA2aLCChJ3Fs1mQmki FngHJPEno87wBLCAoESTYu2gdksAqoS2x8dBdvAK+AuMeXhKmaIDXISJ49NBtrGwcEp4CGx9F odxEHuEn+23WWFKBeUODnzCQtICTPQ3vXzhEDCzALyEs1bZzNPYBSYhaRqFkLVLCRVCxiZVzF qFKcWlaUW6Roa6iUVZaZnlOQmZuboGhqY6eWmFhcnpqfmJCYV6yXn525iBIYmAxDsYPy0LOAQ oyQHk5Iob2jiukghvqT8lMqMxOKM+KLSnNTiQ4wyHBxKEry3ioBygkWp6akVaZk5wCiBSUtw8 CiJ8J4DSfMWFyTmFmemQ6ROMepybFi9/guTEEtefl6qlDjvcZAiAZCijNI8uBGwiL3EKCslzM sIdJQQT0FqUW5mCar8K0ZxDkYlYd4lIFN4MvNK4Da9AjqCCeiIqpdrQI4oSURISTUw7g78ek1 RLqTazOMZi9j7wpJvbOwhzhKrfHq8nW4vZH2d2tktaFh8vKK3bdvXTpYe7uXPoi/Vy4U/FF3+ ufDs3+Mn5T5klp66fkKSuz9oS6iVkISFZ9G2l89P75xWFtmtsrg2yU23UU0gzdgpbaoO371g0 XM6+iExnj8vPRdjDJkwN1uh87ESS3FGoqEWc1FxIgAa/Qmj0wIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1504605073!62289035!1 X-Originating-IP: [134.134.136.100] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 40926 invoked from network); 5 Sep 2017 09:51:15 -0000 Received: from mga07.intel.com (HELO mga07.intel.com) (134.134.136.100) by server-15.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 5 Sep 2017 09:51:15 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 05 Sep 2017 02:51:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,479,1498546800"; d="scan'208";a="897185176" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.80]) by FMSMGA003.fm.intel.com with ESMTP; 05 Sep 2017 02:51:04 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Tue, 5 Sep 2017 17:32:26 +0800 Message-Id: <1504603957-5389-5-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504603957-5389-1-git-send-email-yi.y.sun@linux.intel.com> References: <1504603957-5389-1-git-send-email-yi.y.sun@linux.intel.com> MIME-Version: 1.0 Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, ian.jackson@eu.citrix.com, Yi Sun , julien.grall@arm.com, mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, dgdegra@tycho.nsa.gov, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements main data structures of MBA. Like CAT features, MBA HW info has cos_max which means the max thrtl register number, and thrtl_max which means the max throttle value (delay value). It also has a flag to represent if the throttle value is linear or not. One thrtl register of MBA stores a throttle value for one or more domains. The throttle value means the transaction time between L2 cache and next level memory to be delayed. This patch also implements init flow for MBA and register stub callback functions. Signed-off-by: Yi Sun --- v3: - replace 'psr_val_type' to 'psr_type'. Also, change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'. (suggested by Roger Pau Monné) - replace 'MBA_LINEAR' to 'MBA_LINEAR_MASK' to make the name more clear. (suggested by Roger Pau Monné) - replase 'cat_info'/'mba_info' to 'cat'/'mba' to make the names shorter. (suggested by Roger Pau Monné) - change type of 'linear' to 'bool'. (suggested by Roger Pau Monné) - make format string of printf in one line. (suggested by Roger Pau Monné) v2: - modify commit message to replace 'cos register' to 'thrtl register' to make it accurate. (suggested by Chao Peng) - restore the place of the sentence to assign value to 'feat->cbm_len' because the MBA init flow is splitted out as a separate function in v1. (suggested by Chao Peng) - add comment to explain what the MBA thrtl defaul value '0' stands for. (suggested by Chao Peng) - check 'thrtl_max' under linear mode. It could not be euqal or larger than 100. (suggested by Chao Peng) v1: - rebase codes onto L2 CAT v15. - move comment to appropriate place. (suggested by Chao Peng) - implement 'mba_init_feature' and keep 'cat_init_feature'. (suggested by Chao Peng) - keep 'regs.b' into a local variable to avoid reading CPUID every time. (suggested by Chao Peng) --- xen/arch/x86/psr.c | 140 ++++++++++++++++++++++++++++++++++------ xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 + 3 files changed, 125 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 4166a1c..10776d2 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -27,13 +27,16 @@ * - CMT Cache Monitoring Technology * - COS/CLOS Class of Service. Also mean COS registers. * - COS_MAX Max number of COS for the feature (minus 1) + * - MBA Memory Bandwidth Allocation * - MSRs Machine Specific Registers * - PSR Intel Platform Shared Resource + * - THRTL_MAX Max throttle value (delay value) of MBA */ #define PSR_CMT (1u << 0) #define PSR_CAT (1u << 1) #define PSR_CDP (1u << 2) +#define PSR_MBA (1u << 3) #define CAT_CBM_LEN_MASK 0x1f #define CAT_COS_MAX_MASK 0xffff @@ -60,10 +63,14 @@ */ #define MAX_COS_NUM 2 +#define MBA_LINEAR_MASK (1u << 2) +#define MBA_THRTL_MAX_MASK 0xfff + enum psr_feat_type { FEAT_TYPE_L3_CAT, FEAT_TYPE_L3_CDP, FEAT_TYPE_L2_CAT, + FEAT_TYPE_MBA, FEAT_TYPE_NUM, FEAT_TYPE_UNKNOWN, }; @@ -71,7 +78,6 @@ enum psr_feat_type { /* * This structure represents one feature. * cos_max - The max COS registers number got through CPUID. - * cbm_len - The length of CBM got through CPUID. * cos_reg_val - Array to store the values of COS registers. One entry stores * the value of one COS register. * For L3 CAT and L2 CAT, one entry corresponds to one COS_ID. @@ -80,9 +86,23 @@ enum psr_feat_type { * cos_reg_val[1] (Code). */ struct feat_node { - /* cos_max and cbm_len are common values for all features so far. */ + /* cos_max is common values for all features so far. */ unsigned int cos_max; - unsigned int cbm_len; + + /* Feature specific HW info. */ + union { + struct { + /* The length of CBM got through CPUID. */ + unsigned int cbm_len; + } cat; + + struct { + /* The max throttling value got through CPUID. */ + unsigned int thrtl_max; + bool linear; + } mba; + }; + uint32_t cos_reg_val[MAX_COS_REG_CNT]; }; @@ -161,6 +181,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3; static struct feat_node *feat_l2_cat; +static struct feat_node *feat_mba; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -272,7 +293,7 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm) return true; } -/* CAT common functions implementation. */ +/* Implementation of allocation features' functions. */ static int cat_init_feature(const struct cpuid_leaf *regs, struct feat_node *feat, struct psr_socket_info *info, @@ -288,8 +309,8 @@ static int cat_init_feature(const struct cpuid_leaf *regs, if ( !regs->a || !regs->d ) return -ENOENT; - feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1; feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK); + feat->cat.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1; switch ( type ) { @@ -299,12 +320,12 @@ static int cat_init_feature(const struct cpuid_leaf *regs, return -ENOENT; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - feat->cos_reg_val[0] = cat_default_val(feat->cbm_len); + feat->cos_reg_val[0] = cat_default_val(feat->cat.cbm_len); wrmsrl((type == FEAT_TYPE_L3_CAT ? MSR_IA32_PSR_L3_MASK(0) : MSR_IA32_PSR_L2_MASK(0)), - cat_default_val(feat->cbm_len)); + cat_default_val(feat->cat.cbm_len)); break; @@ -319,11 +340,13 @@ static int cat_init_feature(const struct cpuid_leaf *regs, feat->cos_max = (feat->cos_max - 1) >> 1; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len); - get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len); + get_cdp_code(feat, 0) = cat_default_val(feat->cat.cbm_len); + get_cdp_data(feat, 0) = cat_default_val(feat->cat.cbm_len); - wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len)); - wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len)); + wrmsrl(MSR_IA32_PSR_L3_MASK(0), + cat_default_val(feat->cat.cbm_len)); + wrmsrl(MSR_IA32_PSR_L3_MASK(1), + cat_default_val(feat->cat.cbm_len)); rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val); wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT)); @@ -343,7 +366,50 @@ static int cat_init_feature(const struct cpuid_leaf *regs, printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", cat_feat_name[type], cpu_to_socket(smp_processor_id()), - feat->cos_max, feat->cbm_len); + feat->cos_max, feat->cat.cbm_len); + + return 0; +} + +static int mba_init_feature(const struct cpuid_leaf *regs, + struct feat_node *feat, + struct psr_socket_info *info, + enum psr_feat_type type) +{ + /* No valid value so do not enable feature. */ + if ( !regs->a || !regs->d ) + return -ENOENT; + + if ( type != FEAT_TYPE_MBA ) + return -ENOENT; + + feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK); + if ( feat->cos_max < 1 ) + return -ENOENT; + + feat->mba.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1; + + if ( regs->c & MBA_LINEAR_MASK ) + { + feat->mba.linear = true; + + if ( feat->mba.thrtl_max >= 100 ) + return -ENOENT; + } + + /* We reserve cos=0 as default thrtl (0) which means no delay. */ + feat->cos_reg_val[0] = 0; + wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0); + + /* Add this feature into array. */ + info->features[type] = feat; + + if ( !opt_cpu_info ) + return 0; + + printk(XENLOG_INFO "MBA: enabled on socket %u, cos_max:%u, thrtl_max:%u, linear:%u.\n", + cpu_to_socket(smp_processor_id()), + feat->cos_max, feat->mba.thrtl_max, feat->mba.linear); return 0; } @@ -355,7 +421,7 @@ static bool cat_get_feat_info(const struct feat_node *feat, return false; data[PSR_INFO_IDX_COS_MAX] = feat->cos_max; - data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cbm_len; + data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cat.cbm_len; data[PSR_INFO_IDX_CAT_FLAG] = 0; return true; @@ -421,6 +487,26 @@ static const struct feat_props l2_cat_props = { .write_msr = l2_cat_write_msr, }; +/* MBA props */ +static bool mba_get_feat_info(const struct feat_node *feat, + uint32_t data[], unsigned int array_len) +{ + return false; +} + +static void mba_write_msr(unsigned int cos, uint32_t val, + enum psr_type type) +{ +} + +static const struct feat_props mba_props = { + .cos_num = 1, + .type[0] = PSR_TYPE_MBA_THRTL, + .alt_type = PSR_TYPE_UNKNOWN, + .get_feat_info = mba_get_feat_info, + .write_msr = mba_write_msr, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -456,6 +542,7 @@ static void __init parse_psr_param(char *s) parse_psr_bool(s, val_str, "cmt", PSR_CMT); parse_psr_bool(s, val_str, "cat", PSR_CAT); parse_psr_bool(s, val_str, "cdp", PSR_CDP); + parse_psr_bool(s, val_str, "mba", PSR_MBA); if ( val_str && !strcmp(s, "rmid_max") ) opt_rmid_max = simple_strtoul(val_str, NULL, 0); @@ -862,7 +949,7 @@ static int insert_val_into_array(uint32_t val[], if ( array_len < props->cos_num ) return -ENOSPC; - if ( !psr_check_cbm(feat->cbm_len, new_val) ) + if ( !psr_check_cbm(feat->cat.cbm_len, new_val) ) return -EINVAL; /* @@ -1380,6 +1467,10 @@ static int psr_cpu_prepare(void) (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_mba == NULL && + (feat_mba = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void) unsigned int socket, cpu = smp_processor_id(); struct feat_node *feat; struct cpuid_leaf regs; + uint32_t reg_b; if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) ) goto assoc_init; @@ -1407,7 +1499,8 @@ static void psr_cpu_init(void) spin_lock_init(&info->ref_lock); cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); - if ( regs.b & PSR_RESOURCE_TYPE_L3 ) + reg_b = regs.b; + if ( reg_b & PSR_RESOURCE_TYPE_L3 ) { cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s); @@ -1428,8 +1521,7 @@ static void psr_cpu_init(void) } } - cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); - if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + if ( reg_b & PSR_RESOURCE_TYPE_L2 ) { cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); @@ -1441,6 +1533,18 @@ static void psr_cpu_init(void) feat_l2_cat = feat; } + if ( reg_b & PSR_RESOURCE_TYPE_MBA ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s); + + feat = feat_mba; + feat_mba = NULL; + if ( !mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) ) + feat_props[FEAT_TYPE_MBA] = &mba_props; + else + feat_mba = feat; + } + info->feat_init = true; assoc_init: @@ -1500,7 +1604,7 @@ static int __init psr_presmp_init(void) if ( (opt_psr & PSR_CMT) && opt_rmid_max ) init_psr_cmt(opt_rmid_max); - if ( opt_psr & (PSR_CAT | PSR_CDP) ) + if ( opt_psr & (PSR_CAT | PSR_CDP | PSR_MBA) ) init_psr(); if ( psr_cpu_prepare() ) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 4e08de6..41f1677 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -348,6 +348,7 @@ #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) +#define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index cb3f067..9d14264 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -24,6 +24,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 #define PSR_RESOURCE_TYPE_L2 0x4 +#define PSR_RESOURCE_TYPE_MBA 0x8 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -58,6 +59,7 @@ enum psr_type { PSR_TYPE_L3_CODE, PSR_TYPE_L3_DATA, PSR_TYPE_L2_CBM, + PSR_TYPE_MBA_THRTL, PSR_TYPE_UNKNOWN, };