From patchwork Sat Sep 30 01:39:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9979017 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D7D7F60311 for ; Sat, 30 Sep 2017 02:01:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C5993298AA for ; Sat, 30 Sep 2017 02:01:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA3BB298C5; Sat, 30 Sep 2017 02:01:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4A716298AA for ; Sat, 30 Sep 2017 02:01:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dy73n-0004PZ-JX; Sat, 30 Sep 2017 01:59:19 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dy73m-0004Oy-Kk for xen-devel@lists.xenproject.org; Sat, 30 Sep 2017 01:59:18 +0000 Received: from [85.158.137.68] by server-11.bemta-3.messagelabs.com id 4D/3A-01812-57AFEC95; Sat, 30 Sep 2017 01:59:17 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRWlGSWpSXmKPExsXS1taRolvy61y kwbIua4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNaPj6Ta2ggmGFedam9kaGBerdDFycAgJVEj8 3inTxcjJISHAK3Fk2QxWCDtA4mfvG8YuRi6gkgZGiX3X7jGDJNgE1CUef+1hArFFBJQk7q2az ARSxCzwm1Hi1JZDYAlhAXuJRVNbWEBsFgFViUc/FoFN5RVwl5j+GqJGQkBO4uSxyWBxTgEPiW s9TWwgthBQzZWWtYwQ9YISJ2c+YQE5lBlo8fp5QiBhZgF5ieats5knMArMQlI1C6FqFpKqBYz MqxjVi1OLylKLdI31kooy0zNKchMzc3QNDYz1clOLixPTU3MSk4r1kvNzNzECA5MBCHYwNn9x OsQoycGkJMq7++e5SCG+pPyUyozE4oz4otKc1OJDjDIcHEoSvBEgOcGi1PTUirTMHGCMwKQlO HiURHhtQdK8xQWJucWZ6RCpU4zGHMc2Xf7DxNFx8+4fJiGWvPy8VClx3gKQUgGQ0ozSPLhBsN i9xCgrJczLCHSaEE9BalFuZgmq/CtGcQ5GJWFed5ApPJl5JXD7XgGdwgR0yuSJZ0BOKUlESEk 1MIq94VAINwlRsPJ9mBt+vkJzYsS3uws8l70N+nORcdO/iPehhz/JlWXmOT+ds9ByybT9QtYc b3O/6+S9iV614uHcaO8KHdd6fnn++zOigxOXZGe4VLtkWT7eeDvCupGv6oWFeIcYA6uH5JlXv N+rD/+zSJ6jIujE0Wu6V6M3/EZl6SkftrXHlViKMxINtZiLihMBL37SStgCAAA= X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-9.tower-31.messagelabs.com!1506736754!61764479!1 X-Originating-IP: [134.134.136.100] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26196 invoked from network); 30 Sep 2017 01:59:16 -0000 Received: from mga07.intel.com (HELO mga07.intel.com) (134.134.136.100) by server-9.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 30 Sep 2017 01:59:16 -0000 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP; 29 Sep 2017 18:59:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,455,1500966000"; d="scan'208"; a="1020039006" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.75]) by orsmga003.jf.intel.com with ESMTP; 29 Sep 2017 18:59:12 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Sat, 30 Sep 2017 09:39:14 +0800 Message-Id: <1506735566-5706-5-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506735566-5706-1-git-send-email-yi.y.sun@linux.intel.com> References: <1506735566-5706-1-git-send-email-yi.y.sun@linux.intel.com> MIME-Version: 1.0 Cc: Wei Liu , Yi Sun , Andrew Cooper , Jan Beulich , Chao Peng , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [Xen-devel] [PATCH v5 04/16] x86: a few optimizations to psr codes X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch refines psr codes: 1. Change type of 'cat_init_feature' to 'bool' to remove the pointless returning of error code. 2. Move printk in 'cat_init_feature' to reduce a return path. 3. Define a local variable 'ebx' in 'psr_cpu_init' to reduce calling of 'cpuid_count_leaf()'. 4. Change type of 'write_msr()' to 'uint32_t'. This is needed by later patch: "x86: implement set value flow for MBA". Signed-off-by: Yi Sun Reviewed-by: Roger Pau Monné --- CC: Jan Beulich CC: Andrew Cooper CC: Wei Liu CC: Roger Pau Monné CC: Chao Peng v1: - create this patch to make codes clearer. (suggested by Jan Beulich and Roger Pau Monné) --- xen/arch/x86/psr.c | 55 +++++++++++++++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index ac2ae32..c8db0c1 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -117,7 +117,7 @@ static const struct feat_props { uint32_t data[], unsigned int array_len); /* write_msr is used to write out feature MSR register. */ - void (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type); + uint32_t (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type); } *feat_props[FEAT_TYPE_NUM]; /* @@ -273,10 +273,10 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm) } /* CAT common functions implementation. */ -static int cat_init_feature(const struct cpuid_leaf *regs, - struct feat_node *feat, - struct psr_socket_info *info, - enum psr_feat_type type) +static bool cat_init_feature(const struct cpuid_leaf *regs, + struct feat_node *feat, + struct psr_socket_info *info, + enum psr_feat_type type) { const char *const cat_feat_name[FEAT_TYPE_NUM] = { [FEAT_TYPE_L3_CAT] = "L3 CAT", @@ -286,7 +286,7 @@ static int cat_init_feature(const struct cpuid_leaf *regs, /* No valid value so do not enable feature. */ if ( !regs->a || !regs->d ) - return -ENOENT; + return false; feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1; feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK); @@ -296,7 +296,7 @@ static int cat_init_feature(const struct cpuid_leaf *regs, case FEAT_TYPE_L3_CAT: case FEAT_TYPE_L2_CAT: if ( feat->cos_max < 1 ) - return -ENOENT; + return false; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ feat->cos_reg_val[0] = cat_default_val(feat->cbm_len); @@ -313,7 +313,7 @@ static int cat_init_feature(const struct cpuid_leaf *regs, uint64_t val; if ( feat->cos_max < 3 ) - return -ENOENT; + return false; /* Cut half of cos_max when CDP is enabled. */ feat->cos_max = (feat->cos_max - 1) >> 1; @@ -332,20 +332,18 @@ static int cat_init_feature(const struct cpuid_leaf *regs, } default: - return -ENOENT; + return false; } /* Add this feature into array. */ info->features[type] = feat; - if ( !opt_cpu_info ) - return 0; - - printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", - cat_feat_name[type], cpu_to_socket(smp_processor_id()), - feat->cos_max, feat->cbm_len); + if ( opt_cpu_info ) + printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", + cat_feat_name[type], cpu_to_socket(smp_processor_id()), + feat->cos_max, feat->cbm_len); - return 0; + return true; } static bool cat_get_feat_info(const struct feat_node *feat, @@ -362,10 +360,12 @@ static bool cat_get_feat_info(const struct feat_node *feat, } /* L3 CAT props */ -static void l3_cat_write_msr(unsigned int cos, uint32_t val, - enum psr_type type) +static uint32_t l3_cat_write_msr(unsigned int cos, uint32_t val, + enum psr_type type) { wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val); + + return val; } static const struct feat_props l3_cat_props = { @@ -388,13 +388,15 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat, return true; } -static void l3_cdp_write_msr(unsigned int cos, uint32_t val, - enum psr_type type) +static uint32_t l3_cdp_write_msr(unsigned int cos, uint32_t val, + enum psr_type type) { wrmsrl(((type == PSR_TYPE_L3_DATA) ? MSR_IA32_PSR_L3_MASK_DATA(cos) : MSR_IA32_PSR_L3_MASK_CODE(cos)), val); + + return val; } static const struct feat_props l3_cdp_props = { @@ -407,10 +409,12 @@ static const struct feat_props l3_cdp_props = { }; /* L2 CAT props */ -static void l2_cat_write_msr(unsigned int cos, uint32_t val, - enum psr_type type) +static uint32_t l2_cat_write_msr(unsigned int cos, uint32_t val, + enum psr_type type) { wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val); + + return val; } static const struct feat_props l2_cat_props = { @@ -1410,6 +1414,7 @@ static void psr_cpu_init(void) unsigned int socket, cpu = smp_processor_id(); struct feat_node *feat; struct cpuid_leaf regs; + uint32_t ebx; if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) ) goto assoc_init; @@ -1428,7 +1433,8 @@ static void psr_cpu_init(void) spin_lock_init(&info->ref_lock); cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); - if ( regs.b & PSR_RESOURCE_TYPE_L3 ) + ebx = regs.b; + if ( ebx & PSR_RESOURCE_TYPE_L3 ) { cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s); @@ -1449,8 +1455,7 @@ static void psr_cpu_init(void) } } - cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); - if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + if ( ebx & PSR_RESOURCE_TYPE_L2 ) { cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);