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Iglesias" , Julien Grall , Stefano Stabellini , Volodymyr Babchuk Subject: [Xen-devel] [PATCH v7 01/11] arm: traps: use only least 32 bits of fid in PSCI handler X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP According to SMCCC (ARM DEN 0028B, page 12), function id is stored in least 32 bits of r0/x0 register: The least significant 32-bits are used, and the most significant 32-bits are zero. Implementations must ignore the least significant bits. Signed-off-by: Volodymyr Babchuk Acked-by: Julien Grall --- xen/arch/arm/traps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 701fdc8..0cff83e 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1463,14 +1463,14 @@ static void do_debug_trap(struct cpu_user_regs *regs, unsigned int code) #endif /* helper function for checking arm mode 32/64 bit */ -static inline int psci_mode_check(struct domain *d, register_t fid) +static inline int psci_mode_check(struct domain *d, uint32_t fid) { return !( is_64bit_domain(d)^( (fid & PSCI_0_2_64BIT) >> 30 ) ); } static void do_trap_psci(struct cpu_user_regs *regs) { - register_t fid = PSCI_ARG(regs,0); + uint32_t fid = PSCI_ARG32(regs,0); /* preloading in case psci_mode_check fails */ PSCI_RESULT_REG(regs) = PSCI_INVALID_PARAMETERS;