From patchwork Fri Oct 20 08:28:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 10019245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3A12A602CB for ; Fri, 20 Oct 2017 08:52:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2895A28EA6 for ; Fri, 20 Oct 2017 08:52:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C8D228EC0; Fri, 20 Oct 2017 08:52:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0E3CF28EA6 for ; Fri, 20 Oct 2017 08:52:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e5T0D-00069Y-Fg; Fri, 20 Oct 2017 08:50:01 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e5T0B-00066D-Br for xen-devel@lists.xenproject.org; Fri, 20 Oct 2017 08:49:59 +0000 Received: from [85.158.143.35] by server-9.bemta-6.messagelabs.com id 33/4C-30115-6B8B9E95; Fri, 20 Oct 2017 08:49:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRWlGSWpSXmKPExsXS1tYhr7t1x8t Ig+7f+hbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8btD+uYC7bkVTxdtpexgXFeUBcjB4eQQIXE 5xafLkZODgkBXokjy2awQtj+EvtfPmPvYuQCKmlglLhzeiMzSIJNQF3i8dceJhBbREBJ4t6qy UwgRcwCvxklTm05BJYQFgiU+NmyAMxmEVCVmLX/MguIzSvgLrF8/wpmiA1yEiePTQbbxingIb G39TYjiC0EVDP1zEx2iHpBiZMzn7CAHMoMtHj9PCGQMLOAvETz1tnMExgFZiGpmoVQNQtJ1QJ G5lWMGsWpRWWpRbqGRnpJRZnpGSW5iZk5uoYGZnq5qcXFiempOYlJxXrJ+bmbGIGhyQAEOxgv bww4xCjJwaQkyhtY+TJSiC8pP6UyI7E4I76oNCe1+BCjDAeHkgQv23agnGBRanpqRVpmDjBKY NISHDxKIryPQNK8xQWJucWZ6RCpU4y6HB037/5hEmLJy89LlRLn7QMpEgApyijNgxsBi9hLjL JSwryMQEcJ8RSkFuVmlqDKv2IU52BUEua1AJnCk5lXArfpFdARTEBHsNu/ADmiJBEhJdXAuOt IWQTzT0lrJ9u9/x66ax6fXV+gLDb3ktejxYtYUnQOXf4kmCLAa2xTezPR9Puvo5cU15wwP8+1 aWbkUs/F84zVD84O9v/E57MvPlTpYcjVnwnuG5Y1mh+TcN3wd+km4yC+lX7uwjHsOa5XXPfcn 65w4sjT9zP+mLW5zttQ9Sfv7rmvNakWe5VYijMSDbWYi4oTAQBDHrrTAgAA X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-11.tower-21.messagelabs.com!1508489386!74969590!6 X-Originating-IP: [134.134.136.31] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 18606 invoked from network); 20 Oct 2017 08:49:57 -0000 Received: from mga06.intel.com (HELO mga06.intel.com) (134.134.136.31) by server-11.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 20 Oct 2017 08:49:57 -0000 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 20 Oct 2017 01:49:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,405,1503385200"; d="scan'208";a="162752620" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.75]) by orsmga005.jf.intel.com with ESMTP; 20 Oct 2017 01:49:54 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Fri, 20 Oct 2017 16:28:17 +0800 Message-Id: <1508488108-7071-6-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508488108-7071-1-git-send-email-yi.y.sun@linux.intel.com> References: <1508488108-7071-1-git-send-email-yi.y.sun@linux.intel.com> MIME-Version: 1.0 Cc: Wei Liu , Yi Sun , Andrew Cooper , Jan Beulich , Chao Peng , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [Xen-devel] [PATCH v9 05/16] x86: implement data structure and CPU init flow for MBA X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements main data structures of MBA. Like CAT features, MBA HW info has cos_max which means the max thrtl register number, and thrtl_max which means the max throttle value (delay value). It also has a flag to represent if the throttle value is linear or non-linear. One thrtl register of MBA stores a throttle value for one or more domains. The throttle value means the delay applied to traffic between L2 cache and next cache level. This patch also implements init flow for MBA and register stub callback functions. Signed-off-by: Yi Sun Reviewed-by: Roger Pau Monné Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Andrew Cooper CC: Wei Liu CC: Roger Pau Monné CC: Chao Peng v8: - remove unnecessary line split. (suggested by Jan Beulich) - use MASK_EXTR(). (suggested by Jan Beulich) v7: - modify commit message. (suggested by Jan Beulich) - move the changes about check of 'cat_init_feature' in 'psr_cpu_init' into previous patch. (suggested by Jan Beulich) v6: - restore type of 'mba_write_msr' to 'void'. v5: - move out some CAT codes optimization to a new patch. (suggested by Jan Beulich) - modify commit message. (suggested by Jan Beulich) - change print type of 'linear' to be %d. (suggested by Jan Beulich) - change type of 'mba_write_msr' to uint32_t. - move printk in 'mba_init_feature' to reduce one return path. (suggested by Roger Pau Monné) - move the MBA format string in printk to a new line. (suggested by Roger Pau Monné) v4: - modify commit message. (suggested by Roger Pau Monné) - fix a comment. (suggested by Roger Pau Monné) - join two checks in a single if. (suggested by Roger Pau Monné) - remove redundant initialization of 'feat->cos_reg_val[0]'. (suggested by Roger Pau Monné) - change 'reg_b' to 'ebx'. (suggested by Jan Beulich) - change type of 'mba_init_feature' from 'int' to 'bool'. (suggested by Roger Pau Monné) - change type of 'cat_init_feature' from 'int' to 'bool'. v3: - replace 'psr_val_type' to 'psr_type'. Also, change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'. (suggested by Roger Pau Monné) - replace 'MBA_LINEAR' to 'MBA_LINEAR_MASK' to make the name more clear. (suggested by Roger Pau Monné) - replase 'cat_info'/'mba_info' to 'cat'/'mba' to make the names shorter. (suggested by Roger Pau Monné) - change type of 'linear' to 'bool'. (suggested by Roger Pau Monné) - make format string of printf in one line. (suggested by Roger Pau Monné) v2: - modify commit message to replace 'cos register' to 'thrtl register' to make it accurate. (suggested by Chao Peng) - restore the place of the sentence to assign value to 'feat->cbm_len' because the MBA init flow is splitted out as a separate function in v1. (suggested by Chao Peng) - add comment to explain what the MBA thrtl defaul value '0' stands for. (suggested by Chao Peng) - check 'thrtl_max' under linear mode. It could not be euqal or larger than 100. (suggested by Chao Peng) v1: - rebase codes onto L2 CAT v15. - move comment to appropriate place. (suggested by Chao Peng) - implement 'mba_init_feature' and keep 'cat_init_feature'. (suggested by Chao Peng) - keep 'regs.b' into a local variable to avoid reading CPUID every time. (suggested by Chao Peng) --- xen/arch/x86/psr.c | 127 +++++++++++++++++++++++++++++++++++----- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 + 3 files changed, 114 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 58d203f..872bade 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -27,13 +27,16 @@ * - CMT Cache Monitoring Technology * - COS/CLOS Class of Service. Also mean COS registers. * - COS_MAX Max number of COS for the feature (minus 1) + * - MBA Memory Bandwidth Allocation * - MSRs Machine Specific Registers * - PSR Intel Platform Shared Resource + * - THRTL_MAX Max throttle value (delay value) of MBA */ #define PSR_CMT (1u << 0) #define PSR_CAT (1u << 1) #define PSR_CDP (1u << 2) +#define PSR_MBA (1u << 3) #define CAT_CBM_LEN_MASK 0x1f #define CAT_COS_MAX_MASK 0xffff @@ -60,10 +63,14 @@ */ #define MAX_COS_NUM 2 +#define MBA_LINEAR_MASK (1u << 2) +#define MBA_THRTL_MAX_MASK 0xfff + enum psr_feat_type { FEAT_TYPE_L3_CAT, FEAT_TYPE_L3_CDP, FEAT_TYPE_L2_CAT, + FEAT_TYPE_MBA, FEAT_TYPE_NUM, FEAT_TYPE_UNKNOWN, }; @@ -71,7 +78,6 @@ enum psr_feat_type { /* * This structure represents one feature. * cos_max - The max COS registers number got through CPUID. - * cbm_len - The length of CBM got through CPUID. * cos_reg_val - Array to store the values of COS registers. One entry stores * the value of one COS register. * For L3 CAT and L2 CAT, one entry corresponds to one COS_ID. @@ -80,9 +86,23 @@ enum psr_feat_type { * cos_reg_val[1] (Code). */ struct feat_node { - /* cos_max and cbm_len are common values for all features so far. */ + /* cos_max is common among all features so far. */ unsigned int cos_max; - unsigned int cbm_len; + + /* Feature specific HW info. */ + union { + struct { + /* The length of CBM got through CPUID. */ + unsigned int cbm_len; + } cat; + + struct { + /* The max throttling value got through CPUID. */ + unsigned int thrtl_max; + bool linear; + } mba; + }; + uint32_t cos_reg_val[MAX_COS_REG_CNT]; }; @@ -161,6 +181,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3; static struct feat_node *feat_l2_cat; +static struct feat_node *feat_mba; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -272,7 +293,7 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm) return true; } -/* CAT common functions implementation. */ +/* Implementation of allocation features' functions. */ static bool cat_init_feature(const struct cpuid_leaf *regs, struct feat_node *feat, struct psr_socket_info *info, @@ -288,8 +309,8 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, if ( !regs->a || !regs->d ) return false; - feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1; feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK); + feat->cat.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1; switch ( type ) { @@ -299,12 +320,12 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, return false; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - feat->cos_reg_val[0] = cat_default_val(feat->cbm_len); + feat->cos_reg_val[0] = cat_default_val(feat->cat.cbm_len); wrmsrl((type == FEAT_TYPE_L3_CAT ? MSR_IA32_PSR_L3_MASK(0) : MSR_IA32_PSR_L2_MASK(0)), - cat_default_val(feat->cbm_len)); + cat_default_val(feat->cat.cbm_len)); break; @@ -319,11 +340,11 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, feat->cos_max = (feat->cos_max - 1) >> 1; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len); - get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len); + get_cdp_code(feat, 0) = cat_default_val(feat->cat.cbm_len); + get_cdp_data(feat, 0) = cat_default_val(feat->cat.cbm_len); - wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len)); - wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len)); + wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cat.cbm_len)); + wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cat.cbm_len)); rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val); wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT)); @@ -341,7 +362,44 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, if ( opt_cpu_info ) printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", cat_feat_name[type], cpu_to_socket(smp_processor_id()), - feat->cos_max, feat->cbm_len); + feat->cos_max, feat->cat.cbm_len); + + return true; +} + +static bool mba_init_feature(const struct cpuid_leaf *regs, + struct feat_node *feat, + struct psr_socket_info *info, + enum psr_feat_type type) +{ + /* No valid value so do not enable feature. */ + if ( !regs->a || !regs->d || type != FEAT_TYPE_MBA ) + return false; + + feat->cos_max = min(opt_cos_max, MASK_EXTR(regs->d, CAT_COS_MAX_MASK)); + if ( feat->cos_max < 1 ) + return false; + + feat->mba.thrtl_max = MASK_EXTR(regs->a, MBA_THRTL_MAX_MASK) + 1; + + if ( regs->c & MBA_LINEAR_MASK ) + { + feat->mba.linear = true; + + if ( feat->mba.thrtl_max >= 100 ) + return false; + } + + wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0); + + /* Add this feature into array. */ + info->features[type] = feat; + + if ( opt_cpu_info ) + printk(XENLOG_INFO + "MBA: enabled on socket %u, cos_max:%u, thrtl_max:%u, linear:%d\n", + cpu_to_socket(smp_processor_id()), + feat->cos_max, feat->mba.thrtl_max, feat->mba.linear); return true; } @@ -353,7 +411,7 @@ static bool cat_get_feat_info(const struct feat_node *feat, return false; data[PSR_INFO_IDX_COS_MAX] = feat->cos_max; - data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cbm_len; + data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cat.cbm_len; data[PSR_INFO_IDX_CAT_FLAGS] = 0; return true; @@ -419,6 +477,26 @@ static const struct feat_props l2_cat_props = { .write_msr = l2_cat_write_msr, }; +/* MBA props */ +static bool mba_get_feat_info(const struct feat_node *feat, + uint32_t data[], unsigned int array_len) +{ + return false; +} + +static void mba_write_msr(unsigned int cos, uint32_t val, + enum psr_type type) +{ +} + +static const struct feat_props mba_props = { + .cos_num = 1, + .type[0] = PSR_TYPE_MBA_THRTL, + .alt_type = PSR_TYPE_UNKNOWN, + .get_feat_info = mba_get_feat_info, + .write_msr = mba_write_msr, +}; + static bool __init parse_psr_bool(const char *s, const char *delim, const char *ss, const char *feature, unsigned int mask) @@ -477,7 +555,8 @@ static int __init parse_psr_param(const char *s) } else if ( !parse_psr_bool(s, val_delim, ss, "cmt", PSR_CMT) && !parse_psr_bool(s, val_delim, ss, "cat", PSR_CAT) && - !parse_psr_bool(s, val_delim, ss, "cdp", PSR_CDP) ) + !parse_psr_bool(s, val_delim, ss, "cdp", PSR_CDP) && + !parse_psr_bool(s, val_delim, ss, "mba", PSR_MBA) ) rc = -EINVAL; s = ss + 1; @@ -881,7 +960,7 @@ static int insert_val_into_array(uint32_t val[], if ( array_len < props->cos_num ) return -ENOSPC; - if ( !psr_check_cbm(feat->cbm_len, new_val) ) + if ( !psr_check_cbm(feat->cat.cbm_len, new_val) ) return -EINVAL; /* @@ -1402,6 +1481,10 @@ static int psr_cpu_prepare(void) (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_mba == NULL && + (feat_mba = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1464,6 +1547,18 @@ static void psr_cpu_init(void) feat_l2_cat = feat; } + if ( feat_mask & PSR_RESOURCE_TYPE_MBA ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s); + + feat = feat_mba; + feat_mba = NULL; + if ( mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) ) + feat_props[FEAT_TYPE_MBA] = &mba_props; + else + feat_mba = feat; + } + info->feat_init = true; assoc_init: @@ -1523,7 +1618,7 @@ static int __init psr_presmp_init(void) if ( (opt_psr & PSR_CMT) && opt_rmid_max ) init_psr_cmt(opt_rmid_max); - if ( opt_psr & (PSR_CAT | PSR_CDP) ) + if ( opt_psr & (PSR_CAT | PSR_CDP | PSR_MBA) ) init_psr(); if ( psr_cpu_prepare() ) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index b99c623..a834f3b 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -348,6 +348,7 @@ #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) +#define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index f151fa7..3cf544a 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -24,6 +24,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 #define PSR_RESOURCE_TYPE_L2 0x4 +#define PSR_RESOURCE_TYPE_MBA 0x8 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -58,6 +59,7 @@ enum psr_type { PSR_TYPE_L3_CODE, PSR_TYPE_L3_DATA, PSR_TYPE_L2_CBM, + PSR_TYPE_MBA_THRTL, PSR_TYPE_UNKNOWN, };