From patchwork Fri Nov 17 06:22:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 10062339 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B3D0A6023A for ; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A64CD2A539 for ; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9B3F22A997; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1F2792A990 for ; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa5D-0000dg-UV; Fri, 17 Nov 2017 06:24:59 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa5D-0000cV-9N for xen-devel@lists.xen.org; Fri, 17 Nov 2017 06:24:59 +0000 Received: from [85.158.143.35] by server-7.bemta-6.messagelabs.com id 29/3D-14955-AB08E0A5; Fri, 17 Nov 2017 06:24:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeJIrShJLcpLzFFi42I5YG4Sq7urgS/ KYGMvk8WSj4tZHBg9ju7+zRTAGMWamZeUX5HAmvHu6Gzmgh/6FU8X7mBuYPys2sXIxSEkMJ1R 4mXrS+YuRk4OCQFeiSPLZrBC2AESrz4sZwGxhQSqJI409jCB2GwCyhIXv/aygdgiAtIS1z5fZ gQZxCzwnFliybq/jCAJYYEwiekzvoM1swioSix81gC2gFfAWWLJ3BlQyxQkpjx8D2ZzAsX3vz nIBLHMSeLgumlMExh5FzAyrGJUL04tKkst0rXUSyrKTM8oyU3MzNE1NDDTy00tLk5MT81JTCr WS87P3cQIDAcGINjBeHdTwCFGSQ4mJVFeHnO+KCG+pPyUyozE4oz4otKc1OJDjDIcHEoSvF71 QDnBotT01Iq0zBxgYMKkJTh4lER4C0DSvMUFibnFmekQqVOMxhzPZr5uYOaYdrW1iVmIJS8/L 1VKnLcYpFQApDSjNA9uECxiLjHKSgnzMgKdJsRTkFqUm1mCKv+KUZyDUUmYtxJkCk9mXgncvl dApzABnWJzgxvklJJEhJRUA2PFeR5VM/a903Jnniva5hRytPvSfIWUjezLLaoeP7GZNHMCY4+ rB9+uq3o/Jp50zjbhYuS+lHzwUs2etteG11ZEVLRxt9RUiG69UrEjW0PJKOjqGZmpaaJNE1Im xdguvGIu+c/bfofKhmt8BfGh79tslB+/jVhzcYn6zRMMJzbc5Z1wsMRE2FOJpTgj0VCLuag4E QCj/osjkwIAAA== X-Env-Sender: chao.gao@intel.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1510899867!82378134!10 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 56769 invoked from network); 17 Nov 2017 06:24:57 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-12.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Nov 2017 06:24:57 -0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2017 22:24:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.44,407,1505804400"; d="scan'208"; a="1245165075" Received: from skl-4s-chao.sh.intel.com ([10.239.48.9]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2017 22:24:55 -0800 From: Chao Gao To: xen-devel@lists.xen.org Date: Fri, 17 Nov 2017 14:22:16 +0800 Message-Id: <1510899755-40237-10-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1510899755-40237-1-git-send-email-chao.gao@intel.com> References: <1510899755-40237-1-git-send-email-chao.gao@intel.com> Cc: Lan Tianyu , Kevin Tian , Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Ian Jackson , Tim Deegan , Jan Beulich , Andrew Cooper , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [Xen-devel] [PATCH v4 09/28] x86/vvtd: Set Interrupt Remapping Table Pointer through GCMD X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Software sets SIRTP field of GCMD to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address (IRTA_REG) register. This patch emulates this operation and adds some new fields in VVTD to track info (e.g. the table's gfn and max supported entries) of interrupt remapping table. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- v4: - declare eim_enabled as bool and irt as gfn_t - rename vvtd_handle_gcmd_sirtp() to write_gcmd_sirtp() v3: - ignore unaligned r/w of vt-d hardware registers and return X86EMUL_OK --- xen/drivers/passthrough/vtd/iommu.h | 16 ++++++- xen/drivers/passthrough/vtd/vvtd.c | 86 +++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index f2ef3dd..8579843 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -48,7 +48,8 @@ #define DMAR_IQT_REG 0x88 /* invalidation queue tail */ #define DMAR_IQA_REG 0x90 /* invalidation queue addr */ #define DMAR_IECTL_REG 0xa0 /* invalidation event control register */ -#define DMAR_IRTA_REG 0xb8 /* intr remap */ +#define DMAR_IRTA_REG 0xb8 /* base address of intr remap table */ +#define DMAR_IRTUA_REG 0xbc /* upper address of intr remap table */ #define OFFSET_STRIDE (9) #define dmar_readl(dmar, reg) readl((dmar) + (reg)) @@ -150,6 +151,9 @@ #define DMA_GCMD_SIRTP (((u64)1) << 24) #define DMA_GCMD_CFI (((u64)1) << 23) +/* mask of one-shot bits */ +#define DMA_GCMD_ONE_SHOT_MASK 0x96ffffff + /* GSTS_REG */ #define DMA_GSTS_TES (((u64)1) << 31) #define DMA_GSTS_RTPS (((u64)1) << 30) @@ -157,10 +161,18 @@ #define DMA_GSTS_AFLS (((u64)1) << 28) #define DMA_GSTS_WBFS (((u64)1) << 27) #define DMA_GSTS_QIES (((u64)1) <<26) +#define DMA_GSTS_SIRTPS_SHIFT 24 +#define DMA_GSTS_SIRTPS (((u64)1) << DMA_GSTS_SIRTPS_SHIFT) #define DMA_GSTS_IRES (((u64)1) <<25) -#define DMA_GSTS_SIRTPS (((u64)1) << 24) #define DMA_GSTS_CFIS (((u64)1) <<23) +/* IRTA_REG */ +/* The base of 4KB aligned interrupt remapping table */ +#define DMA_IRTA_ADDR(val) ((val) & ~0xfffULL) +/* The size of remapping table is 2^(x+1), where x is the size field in IRTA */ +#define DMA_IRTA_S(val) (val & 0xf) +#define DMA_IRTA_SIZE(val) (1UL << (DMA_IRTA_S(val) + 1)) + /* PMEN_REG */ #define DMA_PMEN_EPM (((u32)1) << 31) #define DMA_PMEN_PRS (((u32)1) << 0) diff --git a/xen/drivers/passthrough/vtd/vvtd.c b/xen/drivers/passthrough/vtd/vvtd.c index d78d878..f0476fe 100644 --- a/xen/drivers/passthrough/vtd/vvtd.c +++ b/xen/drivers/passthrough/vtd/vvtd.c @@ -36,6 +36,12 @@ #define VVTD_MAX_OFFSET VVTD_FRCD_END struct hvm_hw_vvtd { + bool eim_enabled; + + /* Interrupt remapping table base gfn and the max of entries */ + uint16_t irt_max_entry; + gfn_t irt; + uint32_t regs[VVTD_MAX_OFFSET/sizeof(uint32_t)]; }; @@ -73,6 +79,16 @@ boolean_runtime_param("viommu_verbose", viommu_verbose); #define VVTD_REG_POS(vvtd, offset) &(vvtd->hw.regs[offset/sizeof(uint32_t)]) +static inline void vvtd_set_bit(struct vvtd *vvtd, uint32_t reg, int nr) +{ + __set_bit(nr, VVTD_REG_POS(vvtd, reg)); +} + +static inline void vvtd_clear_bit(struct vvtd *vvtd, uint32_t reg, int nr) +{ + __clear_bit(nr, VVTD_REG_POS(vvtd, reg)); +} + static inline void vvtd_set_reg(struct vvtd *vvtd, uint32_t reg, uint32_t value) { *VVTD_REG_POS(vvtd, reg) = value; @@ -102,6 +118,52 @@ static void *domain_vvtd(const struct domain *d) return NULL; } +static void write_gcmd_sirtp(struct vvtd *vvtd, uint32_t val) +{ + uint64_t irta = vvtd_get_reg_quad(vvtd, DMAR_IRTA_REG); + + if ( !(val & DMA_GCMD_SIRTP) ) + return; + + /* + * Hardware clears this bit when software sets the SIRTPS field in + * the Global Command register and sets it when hardware completes + * the 'Set Interrupt Remap Table Pointer' operation. + */ + vvtd_clear_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_SIRTPS_SHIFT); + + if ( gfn_x(vvtd->hw.irt) != PFN_DOWN(DMA_IRTA_ADDR(irta)) || + vvtd->hw.irt_max_entry != DMA_IRTA_SIZE(irta) ) + { + vvtd->hw.irt = _gfn(PFN_DOWN(DMA_IRTA_ADDR(irta))); + vvtd->hw.irt_max_entry = DMA_IRTA_SIZE(irta); + vvtd->hw.eim_enabled = !!(irta & IRTA_EIME); + vvtd_info("Update IR info (addr=%lx eim=%d size=%d)\n", + gfn_x(vvtd->hw.irt), vvtd->hw.eim_enabled, + vvtd->hw.irt_max_entry); + } + vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_SIRTPS_SHIFT); +} + +static void vvtd_write_gcmd(struct vvtd *vvtd, uint32_t val) +{ + uint32_t orig = vvtd_get_reg(vvtd, DMAR_GSTS_REG); + uint32_t changed; + + orig = orig & DMA_GCMD_ONE_SHOT_MASK; /* reset the one-shot bits */ + changed = orig ^ val; + + if ( !changed ) + return; + + if ( changed & (changed - 1) ) + vvtd_info("Write %x to GCMD (current %x), updating multiple fields", + val, orig); + + if ( changed & DMA_GCMD_SIRTP ) + write_gcmd_sirtp(vvtd, val); +} + static int vvtd_in_range(struct vcpu *v, unsigned long addr) { struct vvtd *vvtd = domain_vvtd(v->domain); @@ -139,6 +201,30 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, vvtd_info("Write offset %x len %d val %lx\n", offset, len, val); + if ( (len != 4 && len != 8) || (offset & (len - 1)) ) + return X86EMUL_OKAY; + + switch ( offset ) + { + case DMAR_GCMD_REG: + vvtd_write_gcmd(vvtd, val); + break; + + case DMAR_IRTA_REG: + vvtd_set_reg(vvtd, offset, val); + if ( len == 4 ) + break; + val = val >> 32; + offset += 4; + /* Fall through */ + case DMAR_IRTUA_REG: + vvtd_set_reg(vvtd, offset, val); + break; + + default: + break; + } + return X86EMUL_OKAY; }