From patchwork Fri Nov 17 06:22:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 10062327 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5490D6023A for ; Fri, 17 Nov 2017 06:27:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 475A32A539 for ; Fri, 17 Nov 2017 06:27:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C2E12A997; Fri, 17 Nov 2017 06:27:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7A2752A539 for ; Fri, 17 Nov 2017 06:27:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa54-0000UJ-2J; Fri, 17 Nov 2017 06:24:50 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa53-0000Tt-7P for xen-devel@lists.xen.org; Fri, 17 Nov 2017 06:24:49 +0000 Received: from [85.158.143.35] by server-9.bemta-6.messagelabs.com id 6E/C7-29052-0B08E0A5; Fri, 17 Nov 2017 06:24:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBIsWRWlGSWpSXmKPExsVywNwkVnd9A1+ Uwa8+a4slHxezODB6HN39mymAMYo1My8pvyKBNePztBNsBU0mFSc/zWdqYHyg0cXIxSEkMJ1R 4uWeRrYuRk4OCQFeiSPLZrBC2AESk+9OYwSxhQSqJD7+awKz2QSUJS5+7QWrFxGQlrj2+TIjy CBmgefMEkvW/QUrEhZwkFjx/hELiM0ioCrxvm0qO4jNK+AksWfBd6gFChJTHr5nBrE5BZwl9r 85yASxzEni4LppTBD1ghInZz4BmsMBtEBdYv08IZAws4C8RPPW2cwTGAVmIamahVA1C0nVAkb mVYzqxalFZalFupZ6SUWZ6RkluYmZObqGBmZ6uanFxYnpqTmJScV6yfm5mxiBockABDsY724K OMQoycGkJMrLY84XJcSXlJ9SmZFYnBFfVJqTWnyIUY+DQ6B3zeoLjAJXzs2dziTFkpefl6okw etVD1QtWJSanlqRlpkDjCSYBgkOHiUR3gKQNG9xQWJucWY6ROoUozHHs5mvG5g5pl1tbWIWAp skJc5bDFIqAFKaUZoHNwgW4ZcYZaWEeRmBjhXiKUgtys0sQZV/xSjOwagkzFsJMoUnM68Ebt8 roFOYgE6xucENckpJIkJKqoFxRd/llTJewsHn1rRN68081Kd+MJKhJyTraFjo4WO1u0R/814w vxDvv6nEVH4vr9+h82tMXqlWFexi7NjzV/SY8tV/7XMccr6esZhl+WTplh3uNy20WKpvMldtV dcqzzlU7h944fCP0hnhLOKGLR5xbMudayNu90tt+SjkahRx7bjw1Zt+fKuVWIozEg21mIuKEw H0tuV76wIAAA== X-Env-Sender: chao.gao@intel.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1510899867!82378134!7 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 55938 invoked from network); 17 Nov 2017 06:24:47 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-12.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Nov 2017 06:24:47 -0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2017 22:24:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.44,407,1505804400"; d="scan'208"; a="1245165055" Received: from skl-4s-chao.sh.intel.com ([10.239.48.9]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2017 22:24:44 -0800 From: Chao Gao To: xen-devel@lists.xen.org Date: Fri, 17 Nov 2017 14:22:13 +0800 Message-Id: <1510899755-40237-7-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1510899755-40237-1-git-send-email-chao.gao@intel.com> References: <1510899755-40237-1-git-send-email-chao.gao@intel.com> MIME-Version: 1.0 Cc: Lan Tianyu , Kevin Tian , Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Ian Jackson , Tim Deegan , Jan Beulich , Andrew Cooper , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [Xen-devel] [PATCH v4 06/28] vtd: clean-up and preparation for vvtd X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch contains following changes: - align register definitions - use MASK_EXTR to define some macros about extended capabilies rather than open-coding the masks - define fields of FECTL and FESTS as uint32_t rather than u64 since FECTL and FESTS are 32 bit registers. No functional changes. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- v4: - Only fix the alignment and defer introducing new definition to when they are needed (Suggested-by Roger Pau Monné) - remove parts of open-coded masks v3: - new --- xen/drivers/passthrough/vtd/iommu.h | 86 +++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 38 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 72c1a2e..db80b31 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -26,28 +26,28 @@ * Intel IOMMU register specification per version 1.0 public spec. */ -#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ -#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ -#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ -#define DMAR_GCMD_REG 0x18 /* Global command register */ -#define DMAR_GSTS_REG 0x1c /* Global status register */ -#define DMAR_RTADDR_REG 0x20 /* Root entry table */ -#define DMAR_CCMD_REG 0x28 /* Context command reg */ -#define DMAR_FSTS_REG 0x34 /* Fault Status register */ -#define DMAR_FECTL_REG 0x38 /* Fault control register */ -#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ -#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ -#define DMAR_FEUADDR_REG 0x44 /* Upper address register */ -#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ -#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ -#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ -#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ -#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ -#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ -#define DMAR_IQH_REG 0x80 /* invalidation queue head */ -#define DMAR_IQT_REG 0x88 /* invalidation queue tail */ -#define DMAR_IQA_REG 0x90 /* invalidation queue addr */ -#define DMAR_IRTA_REG 0xB8 /* intr remap */ +#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ +#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ +#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ +#define DMAR_GCMD_REG 0x18 /* Global command register */ +#define DMAR_GSTS_REG 0x1c /* Global status register */ +#define DMAR_RTADDR_REG 0x20 /* Root entry table */ +#define DMAR_CCMD_REG 0x28 /* Context command reg */ +#define DMAR_FSTS_REG 0x34 /* Fault Status register */ +#define DMAR_FECTL_REG 0x38 /* Fault control register */ +#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ +#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ +#define DMAR_FEUADDR_REG 0x44 /* Upper address register */ +#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ +#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ +#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ +#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ +#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ +#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ +#define DMAR_IQH_REG 0x80 /* invalidation queue head */ +#define DMAR_IQT_REG 0x88 /* invalidation queue tail */ +#define DMAR_IQA_REG 0x90 /* invalidation queue addr */ +#define DMAR_IRTA_REG 0xb8 /* intr remap */ #define OFFSET_STRIDE (9) #define dmar_readl(dmar, reg) readl((dmar) + (reg)) @@ -93,16 +93,26 @@ * Extended Capability Register */ +#define DMA_ECAP_SNP_CTL ((uint64_t)1 << 7) +#define DMA_ECAP_PASS_THRU ((uint64_t)1 << 6) +#define DMA_ECAP_CACHE_HINTS ((uint64_t)1 << 5) +#define DMA_ECAP_EIM ((uint64_t)1 << 4) +#define DMA_ECAP_INTR_REMAP ((uint64_t)1 << 3) +#define DMA_ECAP_DEV_IOTLB ((uint64_t)1 << 2) +#define DMA_ECAP_QUEUED_INVAL ((uint64_t)1 << 1) +#define DMA_ECAP_COHERENT ((uint64_t)1 << 0) + +#define ecap_snp_ctl(e) MASK_EXTR(e, DMA_ECAP_SNP_CTL) +#define ecap_pass_thru(e) MASK_EXTR(e, DMA_ECAP_PASS_THRU) +#define ecap_cache_hints(e) MASK_EXTR(e, DMA_ECAP_CACHE_HINTS) +#define ecap_eim(e) MASK_EXTR(e, DMA_ECAP_EIM) +#define ecap_intr_remap(e) MASK_EXTR(e, DMA_ECAP_INTR_REMAP) +#define ecap_dev_iotlb(e) MASK_EXTR(e, DMA_ECAP_DEV_IOTLB) +#define ecap_queued_inval(e) MASK_EXTR(e, DMA_ECAP_QUEUED_INVAL) +#define ecap_coherent(e) MASK_EXTR(e, DMA_ECAP_COHERENT) + #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) -#define ecap_coherent(e) ((e >> 0) & 0x1) -#define ecap_queued_inval(e) ((e >> 1) & 0x1) -#define ecap_dev_iotlb(e) ((e >> 2) & 0x1) -#define ecap_intr_remap(e) ((e >> 3) & 0x1) -#define ecap_eim(e) ((e >> 4) & 0x1) -#define ecap_cache_hints(e) ((e >> 5) & 0x1) -#define ecap_pass_thru(e) ((e >> 6) & 0x1) -#define ecap_snp_ctl(e) ((e >> 7) & 0x1) /* IOTLB_REG */ #define DMA_TLB_FLUSH_GRANU_OFFSET 60 @@ -164,16 +174,16 @@ #define DMA_CCMD_CAIG_MASK(x) (((u64)x) & ((u64) 0x3 << 59)) /* FECTL_REG */ -#define DMA_FECTL_IM (((u64)1) << 31) +#define DMA_FECTL_IM ((uint32_t)1 << 31) /* FSTS_REG */ -#define DMA_FSTS_PFO ((u64)1 << 0) -#define DMA_FSTS_PPF ((u64)1 << 1) -#define DMA_FSTS_AFO ((u64)1 << 2) -#define DMA_FSTS_APF ((u64)1 << 3) -#define DMA_FSTS_IQE ((u64)1 << 4) -#define DMA_FSTS_ICE ((u64)1 << 5) -#define DMA_FSTS_ITE ((u64)1 << 6) +#define DMA_FSTS_PFO ((uint32_t)1 << 0) +#define DMA_FSTS_PPF ((uint32_t)1 << 1) +#define DMA_FSTS_AFO ((uint32_t)1 << 2) +#define DMA_FSTS_APF ((uint32_t)1 << 3) +#define DMA_FSTS_IQE ((uint32_t)1 << 4) +#define DMA_FSTS_ICE ((uint32_t)1 << 5) +#define DMA_FSTS_ITE ((uint32_t)1 << 6) #define DMA_FSTS_FAULTS DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)