From patchwork Mon Apr 8 10:14:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 10889239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D583113B5 for ; Mon, 8 Apr 2019 10:17:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBC54285A4 for ; Mon, 8 Apr 2019 10:17:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B00E0285C9; Mon, 8 Apr 2019 10:17:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1BA75285A4 for ; Mon, 8 Apr 2019 10:17:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIv-0003oh-D5; Mon, 08 Apr 2019 10:15:05 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIu-0003nO-QS for xen-devel@lists.xenproject.org; Mon, 08 Apr 2019 10:15:04 +0000 X-Inumbo-ID: 2c1f30f0-59e7-11e9-92d7-bc764e045a96 Received: from mail-lj1-x244.google.com (unknown [2a00:1450:4864:20::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 2c1f30f0-59e7-11e9-92d7-bc764e045a96; Mon, 08 Apr 2019 10:15:03 +0000 (UTC) Received: by mail-lj1-x244.google.com with SMTP id r24so10694698ljg.3 for ; Mon, 08 Apr 2019 03:15:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=efYm5WjOCrbLGcCTmR6fzmUDlw+MWdsNeKVZc203yJo=; b=UIrmX4irm9JBFQfpq7mLoJsQpoV8UfaTOoKBqQ987sDvqc5fikOXPfZyXwpa6uxj1V 4Rok/yceQzxKRVZ9Rge8DCcbDmf8WdMMXw1fYKy4IwMKp8MnhwtODbVNsBvjMVdn86I/ XT1QqDevDozA/r0lzIKiyHIxUI8S+DbmX+yn4Mh+cur3LUyqL+KvSKW0Gn0g97LaCwVw EsOVPwMq23ws+jOu2HNes3umv9OPeC/OoLZSriHRIDNZpJlEQYeNBPR3pbco8DR0mPCv /YCWnB7rCjhugim8yfuaItudhaBgdvWW25LUBZKYYiVh0VNocczcsXg5TQKhjFC4ZgeQ e8RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=efYm5WjOCrbLGcCTmR6fzmUDlw+MWdsNeKVZc203yJo=; b=bHz9YUzuJsCEuh4zCutFBzh8ojqpWa/9k8c4V4HbCMDESbb7fGqawBC8WQpwI4BCUm /gmTx7A14zbPEr+BD2ddBHEZDmhkLHYPlZtTUKjgE2bFaVA7rDnCrO4Hlqwuhbaa4McV CJCDMxQyQPL8PWhbCNGdpe9xMYN88E0fSYMLprahrw0HES6dxmp9cj8vm6mUaXWDLAHW +2EQVTNP2TC3A4MAnCJ62tYwXFs3VDG+MEw8bQsGvBOYTlkR5hVTomfzLq2vnpX+Ipqu ZvxSV0+w0QR2VqooZ1GuahqPp+yuJlPkUVkAYitd3g7pgGxxLcGLm89eUdh/n0eswjKf Iy/g== X-Gm-Message-State: APjAAAXK8/EnhjGDj16CNkgSsWnAkGYOptg8qRondGQS4mJv7P2b1t1V D4HGOWtE6fgiQ6VaeFl28kvmUp2Q4to= X-Google-Smtp-Source: APXvYqztAuFZq1vu8hk/y1Avafygw2SQN53Mh5/lQF3iwPo/zzBnoquVuZGDM1DwUbyOAvs/P2NiWQ== X-Received: by 2002:a2e:8648:: with SMTP id i8mr15339321ljj.166.1554718501705; Mon, 08 Apr 2019 03:15:01 -0700 (PDT) Received: from otyshchenko.kyiv.epam.com (ll-22.209.223.85.sovam.net.ua. [85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.15.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:15:01 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:47 +0300 Message-Id: <1554718489-11318-4-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 3/5] xen/arm: drivers: scif: Add support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko For the driver to be able to handle SCIFA interface as well, this patch just adds the following: - SCIFA related macros - New element in "port_params" array to keep SCIFA specific things - SCIFA compatible string This patch makes possible to use existing driver for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only adds SCIFA support --- xen/drivers/char/scif-uart.c | 18 +++++++++++++++++- xen/include/asm-arm/scif-uart.h | 40 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 958f717..94cb230 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -1,7 +1,7 @@ /* * xen/drivers/char/scif-uart.c * - * Driver for SCIF (Serial communication interface with FIFO) + * Driver for SCIF(A) (Serial communication interface with FIFO (A)) * compatible UART. * * Oleksandr Tyshchenko @@ -46,6 +46,7 @@ static struct scif_uart { enum port_types { SCIF_PORT, + SCIFA_PORT, NR_PORTS, }; @@ -74,6 +75,20 @@ static const struct port_params port_params[NR_PORTS] = .irq_flags = SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, .fifo_size = 16, }, + + [SCIFA_PORT] = + { + .status_reg = SCIFA_SCASSR, + .tx_fifo_reg = SCIFA_SCAFTDR, + .rx_fifo_reg = SCIFA_SCAFRDR, + .overrun_reg = SCIFA_SCASSR, + .overrun_mask = SCASSR_ORER, + .error_mask = SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER | + SCASSR_ORER, + .irq_flags = SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_ERIE | + SCASCR_BRIE, + .fifo_size = 64, + }, }; static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) @@ -279,6 +294,7 @@ static struct uart_driver __read_mostly scif_uart_driver = { static const struct dt_device_match scif_uart_dt_match[] __initconst = { { .compatible = "renesas,scif", .data = (void *)SCIF_PORT }, + { .compatible = "renesas,scifa", .data = (void *)SCIFA_PORT }, { /* sentinel */ }, }; diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uart.h index c343f2f..bce3404 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -2,7 +2,7 @@ * xen/include/asm-arm/scif-uart.h * * Common constant definition between early printk and the UART driver - * for the SCIF compatible UART. + * for the SCIF(A) compatible UART. * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -21,7 +21,7 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H -/* Register offsets */ +/* Register offsets (SCIF) */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ #define SCIF_SCSCR (0x08) /* Serial control register */ @@ -79,6 +79,42 @@ #define SCFCR_TTRG10 (SCFCR_TTRG1) #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) +/* Register offsets (SCIFA) */ +#define SCIFA_SCASMR (0x00) /* Serial mode register */ +#define SCIFA_SCABRR (0x04) /* Bit rate register */ +#define SCIFA_SCASCR (0x08) /* Serial control register */ +#define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ +#define SCIFA_SCAFER (0x10) /* FIFO error count register */ +#define SCIFA_SCASSR (0x14) /* Serial status register */ +#define SCIFA_SCAFCR (0x18) /* FIFO control register */ +#define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ +#define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ +#define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ +#define SCIFA_SCAPCR (0x30) /* Serial port control register */ +#define SCIFA_SCAPDR (0x34) /* Serial port data register */ + +/* Serial Control Register (SCASCR) */ +#define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ +#define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ +#define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enable */ +#define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ +#define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ +#define SCASCR_TE (1 << 5) /* Transmit Enable */ +#define SCASCR_RE (1 << 4) /* Receive Enable */ +#define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ + +/* Serial Status Register (SCASSR) */ +#define SCASSR_ORER (1 << 9) /* Overrun Error */ +#define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ +#define SCASSR_ER (1 << 7) /* Receive Error */ +#define SCASSR_TEND (1 << 6) /* Transmission End */ +#define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ +#define SCASSR_BRK (1 << 4) /* Break Detect */ +#define SCASSR_FER (1 << 3) /* Framing Error */ +#define SCASSR_PER (1 << 2) /* Parity Error */ +#define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ +#define SCASSR_DR (1 << 0) /* Receive Data Ready */ + #endif /* __ASM_ARM_SCIF_UART_H */ /*