From patchwork Thu Apr 25 20:23:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Druzhinin X-Patchwork-Id: 10917755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DB7814B6 for ; Thu, 25 Apr 2019 20:26:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F25B28CBE for ; Thu, 25 Apr 2019 20:26:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4333B28CC6; Thu, 25 Apr 2019 20:26:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C947828CBE for ; Thu, 25 Apr 2019 20:26:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hJkuy-0001Ii-NT; Thu, 25 Apr 2019 20:24:28 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hJkux-0001IT-LR for xen-devel@lists.xenproject.org; Thu, 25 Apr 2019 20:24:27 +0000 X-Inumbo-ID: 1eebf84b-6798-11e9-843c-bc764e045a96 Received: from SMTP03.CITRIX.COM (unknown [162.221.156.55]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 1eebf84b-6798-11e9-843c-bc764e045a96; Thu, 25 Apr 2019 20:24:26 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,394,1549929600"; d="scan'208";a="84450965" From: Igor Druzhinin To: Date: Thu, 25 Apr 2019 21:23:56 +0100 Message-ID: <1556223838-5176-2-git-send-email-igor.druzhinin@citrix.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556223838-5176-1-git-send-email-igor.druzhinin@citrix.com> References: <1556223838-5176-1-git-send-email-igor.druzhinin@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v3 1/3] OvmfPkg/XenSupport: remove usage of prefetchable PCI host bridge aperture X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Igor Druzhinin , ard.biesheuvel@linaro.org, jordan.l.justen@intel.com, julien.grall@arm.com, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, lersek@redhat.com Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This aperture doesn't exist in QEMU-XEN and hvmloader places BARs in arbitrary order disregarding prefetchable bit. This makes prefetchable and non-prefetchable BARs to follow each other that's quite likely with PCI passthrough devices. In that case, the existing code, that tries to work out aperture boundaries by reading hvmloader BAR placement, will report a bogus prefetchable aperture which overlaps with the regular one. It will eventually trigger an assertion in DXE PCI initialization code. Do the same thing as OVMF on QEMU-KVM and pass a non-existing aperture there. It's not necessary to pass additional allocation flags as we set ResourceAssigned flag on the root bridge which means they will be ignored. Reviewed-by: Anthony PERARD Signed-off-by: Igor Druzhinin --- OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 34 ++++++++++----------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c index afb2c5e..354b0a5 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c +++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c @@ -60,9 +60,7 @@ PcatPciRootBridgeParseBars ( IN UINTN BarOffsetEnd, IN PCI_ROOT_BRIDGE_APERTURE *Io, IN PCI_ROOT_BRIDGE_APERTURE *Mem, - IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, - IN PCI_ROOT_BRIDGE_APERTURE *PMem, - IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G ) { @@ -123,11 +121,7 @@ PcatPciRootBridgeParseBars ( // Length = ((~Length) + 1) & 0xffffffff; - if ((Value & BIT3) == BIT3) { - MemAperture = PMem; - } else { - MemAperture = Mem; - } + MemAperture = Mem; } else { // // 64bit @@ -143,11 +137,7 @@ PcatPciRootBridgeParseBars ( Length = Length | LShiftU64 ((UINT64) UpperValue, 32); Length = (~Length) + 1; - if ((Value & BIT3) == BIT3) { - MemAperture = PMemAbove4G; - } else { - MemAperture = MemAbove4G; - } + MemAperture = MemAbove4G; } Limit = Base + Length - 1; @@ -164,6 +154,8 @@ PcatPciRootBridgeParseBars ( } } +STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 }; + PCI_ROOT_BRIDGE * ScanForRootBridges ( UINTN *NumberOfRootBridges @@ -180,7 +172,7 @@ ScanForRootBridges ( UINT64 Base; UINT64 Limit; UINT64 Value; - PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture; + PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, *MemAperture; PCI_ROOT_BRIDGE *RootBridges; UINTN BarOffsetEnd; @@ -200,9 +192,7 @@ ScanForRootBridges ( ZeroMem (&Io, sizeof (Io)); ZeroMem (&Mem, sizeof (Mem)); ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); - ZeroMem (&PMem, sizeof (PMem)); - ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); - Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64; + Io.Base = Mem.Base = MemAbove4G.Base = MAX_UINT64; // // Scan all the PCI devices on the primary bus of the PCI root bridge // @@ -307,16 +297,17 @@ ScanForRootBridges ( // // Get the Prefetchable Memory range that the PPB is decoding + // and merge it into Memory range // Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f; Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16; Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0) << 16) | 0xfffff; - MemAperture = &PMem; + MemAperture = &Mem; if (Value == BIT0) { Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32); Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32); - MemAperture = &PMemAbove4G; + MemAperture = &MemAbove4G; } if (Base < Limit) { if (MemAperture->Base > Base) { @@ -367,8 +358,7 @@ ScanForRootBridges ( OFFSET_OF (PCI_TYPE00, Device.Bar), BarOffsetEnd, &Io, - &Mem, &MemAbove4G, - &PMem, &PMemAbove4G + &Mem, &MemAbove4G ); // @@ -440,7 +430,7 @@ ScanForRootBridges ( InitRootBridge ( Attributes, Attributes, 0, (UINT8) PrimaryBus, (UINT8) SubBus, - &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G, + &Io, &Mem, &MemAbove4G, &mNonExistAperture, &mNonExistAperture, &RootBridges[*NumberOfRootBridges] ); RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;