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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id p11sm776322ljg.56.2019.08.23.12.35.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Aug 2019 12:35:22 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Fri, 23 Aug 2019 22:34:52 +0300 Message-Id: <1566588892-5305-1-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 Subject: [Xen-devel] [PATCH] [RFC V2] xen/arm: Restrict "p2m_ipa_bits" according to the IOMMU requirements X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org, Volodymyr_Babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Oleksandr Tyshchenko There is a strict requirement for the IOMMU which wants to share the P2M table with the CPU. The IOMMU's Stage-2 input size must be equal to the P2M IPA size. It is not a problem when the IOMMU can support all values the CPU supports. In that case, the IOMMU driver would just use any "p2m_ipa_bits" value as is. But, there are cases when not. In order to make P2M sharing possible on the platforms which IPMMUs have a limitation in maximum Stage-2 input size introduce the following logic. First initialize the IOMMU subsystem and gather requirements regarding the maximum IPA bits supported by each IOMMU device to figure out the minimum value among them. In the P2M code, take into the account the IOMMU requirements and choose suitable "pa_range" according to the restricted "p2m_ipa_bits". Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Still RFC: 1. Patch assumes that IPMMU support is already in. 2. Not checked for the SMMU. Changes since RFC V1 [1]: - Don't update p2m_ipa_bits by the IOMMU drivers directly, introduce p2m_restrict_ipa_bits() - Clarify patch subject/description - Add more comments to code - Check for equivalent "pabits" in setup_virt_paging() - Remove ASSERTs from the SMMU and IPMMU drivers [1] https://lists.xenproject.org/archives/html/xen-devel/2019-08/msg02078.html --- xen/arch/arm/p2m.c | 33 ++++++++++++++++++++++++++++++-- xen/arch/arm/setup.c | 11 +++++++++-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 19 ++++-------------- xen/drivers/passthrough/arm/smmu.c | 16 ++++++++-------- xen/include/asm-arm/p2m.h | 8 ++++++++ 5 files changed, 60 insertions(+), 27 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2374e92..f742d9c 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -34,7 +34,8 @@ static unsigned int __read_mostly max_vmid = MAX_VMID_8_BIT; #define P2M_ROOT_PAGES (1<> ID2_IAS_SHIFT) & ID2_IAS_MASK); smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); - /* Xen: Stage-2 input size has to match p2m_ipa_bits. */ - if (size < p2m_ipa_bits) { - dev_err(smmu->dev, - "P2M IPA size not supported (P2M=%u SMMU=%lu)!\n", - p2m_ipa_bits, size); - return -ENODEV; - } - smmu->s2_input_size = p2m_ipa_bits; + /* + * Xen: + * Set maximum Stage-2 input size supported by the SMMU. We expect + * the P2M code will take into the account the IOMMU requirements and + * choose suitable "pa_range". + */ + p2m_restrict_ipa_bits(size); + smmu->s2_input_size = size; #if 0 /* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */ #ifdef CONFIG_64BIT diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index f970c53..cdcf83a 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -165,6 +165,14 @@ void p2m_altp2m_check(struct vcpu *v, uint16_t idx) /* Not supported on ARM. */ } +/* + * Helper to restrict "p2m_ipa_bits" according the IOMMU requirements. + * + * Each IOMMU driver should report the maximum IPA bits (Stage-2 input size) + * it can support. + */ +void p2m_restrict_ipa_bits(unsigned int iommu_ipa_bits); + /* Second stage paging setup, to be called on all CPUs */ void setup_virt_paging(void);