From patchwork Tue May 3 17:26:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12836036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF94EC433EF for ; Tue, 3 May 2022 17:26:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.319814.540224 (Exim 4.92) (envelope-from ) id 1nlwHz-0006j0-9v; Tue, 03 May 2022 17:26:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 319814.540224; Tue, 03 May 2022 17:26:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlwHz-0006it-6l; Tue, 03 May 2022 17:26:19 +0000 Received: by outflank-mailman (input) for mailman id 319814; Tue, 03 May 2022 17:26:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlwHx-0006J7-6v for xen-devel@lists.xenproject.org; Tue, 03 May 2022 17:26:17 +0000 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [2a00:1450:4864:20::22b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 231db891-cb06-11ec-8fc4-03012f2f19d4; Tue, 03 May 2022 19:26:16 +0200 (CEST) Received: by mail-lj1-x22b.google.com with SMTP id g16so17388079lja.3 for ; Tue, 03 May 2022 10:26:16 -0700 (PDT) Received: from otyshchenko.router ([212.22.223.21]) by smtp.gmail.com with ESMTPSA id x18-20020a2e9dd2000000b0024f275bb06asm1395134ljj.3.2022.05.03.10.26.12 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 May 2022 10:26:13 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 231db891-cb06-11ec-8fc4-03012f2f19d4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f65g7NWnRsWANdfet5Rqx3TxwkiQFjNC9zdZg7FLBDU=; b=SYeHmTXCVvsqvobnc8rIqi9fwFmANSJZzvNBqSCU3btsfPZYpY1/ZdgIw6Rkr3/0/K RE5qwDZm4ArUQVR3XtbEMDgnraaxN7Gjd5tcwKbshzJ9NPIHWZ+pdFKDB5lhm1JBJ3rk aGQVwJ8XWuT/zM1gaBYl7KN4oog1qhbFD+STauhec9IGldIt8XK4Ls0Cha291Kk6WoMJ VHOAiQ9eqmn2g40WqSmj0XRWQAceqp50gsN9ybL3rTp+VMGqcKGhA8/gvnh+6BBk4Zv/ rlSJD5eh+d3xr/sVbtFIzd70cK+jG5LS7BUp5hn79CxA7fdgzGtrU4wcJmlqs9BbfTJf mKAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f65g7NWnRsWANdfet5Rqx3TxwkiQFjNC9zdZg7FLBDU=; b=AN+ZlKZFUabhz/BbAQv8dZeve1YRknMn/FRMQ+2c9rSwcBG3IQhkR0Ss02tE9HUTFp o3uAuqWjJqBsGYF/wHSYPBNxLK+Ce0cm5RfqULRWNn8Y80ROeHMR42pK8rEJLmpOxoZx udZ7waRCFLEeYp6n76oAKgRKEL5Z2jNgGrbl3opAEG1c9+ycPnR/CdVcwOkAPTAvJ31H O9owTCPVqjJSIqOnw/t/Bufda5U3sW4a/ipYHjL5YoxGaMdf7zoMXqR117LJdrf3ghkw t58nVHDkpN+77lK2dgSLw7GRRiero0Fr2VRH7LjVekOi/OTPgRHSKj1M/T7QdvoY91ec FV0Q== X-Gm-Message-State: AOAM532bk6NIBquZsoG3gaJLcOu4r/bWM72THAMyk5ZrVDkYewvhfBvQ 4WdZHxl/78X07bbUldeBlnfxyWz4Sws= X-Google-Smtp-Source: ABdhPJzLkBZTJwKS1QtEVBgQdPUcpKoo+faBrTFSXDQzye/esbr7nKb7add+WCgeHTd2sf84IZiWSw== X-Received: by 2002:a05:651c:211b:b0:24f:4da2:6e3c with SMTP id a27-20020a05651c211b00b0024f4da26e3cmr9388996ljq.37.1651598774845; Tue, 03 May 2022 10:26:14 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Wei Liu , Anthony PERARD , Juergen Gross , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Oleksandr Tyshchenko Subject: [PATCH V8 2/2] libxl: Introduce basic virtio-mmio support on Arm Date: Tue, 3 May 2022 20:26:03 +0300 Message-Id: <1651598763-12162-3-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651598763-12162-1-git-send-email-olekstysh@gmail.com> References: <1651598763-12162-1-git-send-email-olekstysh@gmail.com> MIME-Version: 1.0 From: Julien Grall This patch introduces helpers to allocate Virtio MMIO params (IRQ and memory region) and create specific device node in the Guest device-tree with allocated params. In order to deal with multiple Virtio devices, reserve corresponding ranges. For now, we reserve 1MB for memory regions and 10 SPIs. As these helpers should be used for every Virtio device attached to the Guest, call them for Virtio disk(s). Please note, with statically allocated Virtio IRQs there is a risk of a clash with a physical IRQs of passthrough devices. For the first version, it's fine, but we should consider allocating the Virtio IRQs automatically. Thankfully, we know in advance which IRQs will be used for passthrough to be able to choose non-clashed ones. Signed-off-by: Julien Grall Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Stefano Stabellini --- Please note, this is a split/cleanup/hardening of Julien's PoC: "Add support for Guest IO forwarding to a device emulator" Changes RFC -> V1: - was squashed with: "[RFC PATCH V1 09/12] libxl: Handle virtio-mmio irq in more correct way" "[RFC PATCH V1 11/12] libxl: Insert "dma-coherent" property into virtio-mmio device node" "[RFC PATCH V1 12/12] libxl: Fix duplicate memory node in DT" - move VirtIO MMIO #define-s to xen/include/public/arch-arm.h Changes V1 -> V2: - update the author of a patch Changes V2 -> V3: - no changes Changes V3 -> V4: - no changes Changes V4 -> V5: - split the changes, change the order of the patches - drop an extra "virtio" configuration option - update patch description - use CONTAINER_OF instead of own implementation - reserve ranges for Virtio MMIO params and put them in correct location - create helpers to allocate Virtio MMIO params, add corresponding sanity-сhecks - add comment why MMIO size 0x200 is chosen - update debug print - drop Wei's T-b Changes V5 -> V6: - rebase on current staging Changes V6 -> V7: - rebase on current staging - add T-b and R-b tags - update according to the recent changes to "libxl: Add support for Virtio disk configuration" Changes V7 -> V8: - drop T-b and R-b tags - make virtio_mmio_base/irq global variables to be local in libxl__arch_domain_prepare_config() and initialize them at the beginning of the function, then rework alloc_virtio_mmio_base/irq() to take a pointer to virtio_mmio_base/irq variables as an argument - update according to the recent changes to "libxl: Add support for Virtio disk configuration" --- tools/libs/light/libxl_arm.c | 118 +++++++++++++++++++++++++++++++++++++++++- xen/include/public/arch-arm.h | 7 +++ 2 files changed, 123 insertions(+), 2 deletions(-) diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index eef1de0..37403a2 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -8,6 +8,46 @@ #include #include +/* + * There is no clear requirements for the total size of Virtio MMIO region. + * The size of control registers is 0x100 and device-specific configuration + * registers starts at the offset 0x100, however it's size depends on the device + * and the driver. Pick the biggest known size at the moment to cover most + * of the devices (also consider allowing the user to configure the size via + * config file for the one not conforming with the proposed value). + */ +#define VIRTIO_MMIO_DEV_SIZE xen_mk_ullong(0x200) + +static uint64_t alloc_virtio_mmio_base(libxl__gc *gc, uint64_t *virtio_mmio_base) +{ + uint64_t base = *virtio_mmio_base; + + /* Make sure we have enough reserved resources */ + if ((base + VIRTIO_MMIO_DEV_SIZE > + GUEST_VIRTIO_MMIO_BASE + GUEST_VIRTIO_MMIO_SIZE)) { + LOG(ERROR, "Ran out of reserved range for Virtio MMIO BASE 0x%"PRIx64"\n", + base); + return 0; + } + *virtio_mmio_base += VIRTIO_MMIO_DEV_SIZE; + + return base; +} + +static uint32_t alloc_virtio_mmio_irq(libxl__gc *gc, uint32_t *virtio_mmio_irq) +{ + uint32_t irq = *virtio_mmio_irq; + + /* Make sure we have enough reserved resources */ + if (irq > GUEST_VIRTIO_MMIO_SPI_LAST) { + LOG(ERROR, "Ran out of reserved range for Virtio MMIO IRQ %u\n", irq); + return 0; + } + (*virtio_mmio_irq)++; + + return irq; +} + static const char *gicv_to_string(libxl_gic_version gic_version) { switch (gic_version) { @@ -26,8 +66,10 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, { uint32_t nr_spis = 0; unsigned int i; - uint32_t vuart_irq; - bool vuart_enabled = false; + uint32_t vuart_irq, virtio_irq = 0; + bool vuart_enabled = false, virtio_enabled = false; + uint64_t virtio_mmio_base = GUEST_VIRTIO_MMIO_BASE; + uint32_t virtio_mmio_irq = GUEST_VIRTIO_MMIO_SPI_FIRST; /* * If pl011 vuart is enabled then increment the nr_spis to allow allocation @@ -39,6 +81,30 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, vuart_enabled = true; } + for (i = 0; i < d_config->num_disks; i++) { + libxl_device_disk *disk = &d_config->disks[i]; + + if (disk->specification == LIBXL_DISK_SPECIFICATION_VIRTIO) { + disk->base = alloc_virtio_mmio_base(gc, &virtio_mmio_base); + if (!disk->base) + return ERROR_FAIL; + + disk->irq = alloc_virtio_mmio_irq(gc, &virtio_mmio_irq); + if (!disk->irq) + return ERROR_FAIL; + + if (virtio_irq < disk->irq) + virtio_irq = disk->irq; + virtio_enabled = true; + + LOG(DEBUG, "Allocate Virtio MMIO params for Vdev %s: IRQ %u BASE 0x%"PRIx64, + disk->vdev, disk->irq, disk->base); + } + } + + if (virtio_enabled) + nr_spis += (virtio_irq - 32) + 1; + for (i = 0; i < d_config->b_info.num_irqs; i++) { uint32_t irq = d_config->b_info.irqs[i]; uint32_t spi; @@ -58,6 +124,13 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, return ERROR_FAIL; } + /* The same check as for vpl011 */ + if (virtio_enabled && + (irq >= GUEST_VIRTIO_MMIO_SPI_FIRST && irq <= virtio_irq)) { + LOG(ERROR, "Physical IRQ %u conflicting with Virtio MMIO IRQ range\n", irq); + return ERROR_FAIL; + } + if (irq < 32) continue; @@ -787,6 +860,39 @@ static int make_vpci_node(libxl__gc *gc, void *fdt, return 0; } + +static int make_virtio_mmio_node(libxl__gc *gc, void *fdt, + uint64_t base, uint32_t irq) +{ + int res; + gic_interrupt intr; + /* Placeholder for virtio@ + a 64-bit number + \0 */ + char buf[24]; + + snprintf(buf, sizeof(buf), "virtio@%"PRIx64, base); + res = fdt_begin_node(fdt, buf); + if (res) return res; + + res = fdt_property_compat(gc, fdt, 1, "virtio,mmio"); + if (res) return res; + + res = fdt_property_regs(gc, fdt, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_CELLS, + 1, base, VIRTIO_MMIO_DEV_SIZE); + if (res) return res; + + set_interrupt(intr, irq, 0xf, DT_IRQ_TYPE_EDGE_RISING); + res = fdt_property_interrupts(gc, fdt, &intr, 1); + if (res) return res; + + res = fdt_property(fdt, "dma-coherent", NULL, 0); + if (res) return res; + + res = fdt_end_node(fdt); + if (res) return res; + + return 0; +} + static const struct arch_info *get_arch_info(libxl__gc *gc, const struct xc_dom_image *dom) { @@ -988,6 +1094,7 @@ static int libxl__prepare_dtb(libxl__gc *gc, libxl_domain_config *d_config, size_t fdt_size = 0; int pfdt_size = 0; libxl_domain_build_info *const info = &d_config->b_info; + unsigned int i; const libxl_version_info *vers; const struct arch_info *ainfo; @@ -1094,6 +1201,13 @@ next_resize: if (d_config->num_pcidevs) FDT( make_vpci_node(gc, fdt, ainfo, dom) ); + for (i = 0; i < d_config->num_disks; i++) { + libxl_device_disk *disk = &d_config->disks[i]; + + if (disk->specification == LIBXL_DISK_SPECIFICATION_VIRTIO) + FDT( make_virtio_mmio_node(gc, fdt, disk->base, disk->irq) ); + } + if (pfdt) FDT( copy_partial_fdt(gc, fdt, pfdt) ); diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index ab05fe1..c8b6058 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -407,6 +407,10 @@ typedef uint64_t xen_callback_t; /* Physical Address Space */ +/* Virtio MMIO mappings */ +#define GUEST_VIRTIO_MMIO_BASE xen_mk_ullong(0x02000000) +#define GUEST_VIRTIO_MMIO_SIZE xen_mk_ullong(0x00100000) + /* * vGIC mappings: Only one set of mapping is used by the guest. * Therefore they can overlap. @@ -493,6 +497,9 @@ typedef uint64_t xen_callback_t; #define GUEST_VPL011_SPI 32 +#define GUEST_VIRTIO_MMIO_SPI_FIRST 33 +#define GUEST_VIRTIO_MMIO_SPI_LAST 43 + /* PSCI functions */ #define PSCI_cpu_suspend 0 #define PSCI_cpu_off 1