| Message ID | 16fb328e06f6b99d967fa7d186a4c0aaa986050e.1677838213.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Do basic initialization things | expand |
On 03/03/2023 10:24 am, Oleksii Kurochko wrote: > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> > diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S > index adf5d6c74a..8887f0cbd4 100644 > --- a/xen/arch/riscv/riscv64/head.S > +++ b/xen/arch/riscv/riscv64/head.S > @@ -18,6 +19,14 @@ ENTRY(start) > li t0, SSTATUS_FS > csrc CSR_SSTATUS, t0 > > + /* Clear the BSS */ > + la t3, __bss_start > + la t4, __bss_end > +.L_clear_bss: > + REG_S zero, (t3) > + add t3, t3, __SIZEOF_POINTER__ > + bltu t3, t4, .L_clear_bss Using t3/t4 is fine, but it would also have been fine to use t0/t1. ~Andrew
On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote: > On 03/03/2023 10:24 am, Oleksii Kurochko wrote: > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> > > > diff --git a/xen/arch/riscv/riscv64/head.S > > b/xen/arch/riscv/riscv64/head.S > > index adf5d6c74a..8887f0cbd4 100644 > > --- a/xen/arch/riscv/riscv64/head.S > > +++ b/xen/arch/riscv/riscv64/head.S > > @@ -18,6 +19,14 @@ ENTRY(start) > > li t0, SSTATUS_FS > > csrc CSR_SSTATUS, t0 > > > > + /* Clear the BSS */ > > + la t3, __bss_start > > + la t4, __bss_end > > +.L_clear_bss: > > + REG_S zero, (t3) > > + add t3, t3, __SIZEOF_POINTER__ > > + bltu t3, t4, .L_clear_bss > > Using t3/t4 is fine, but it would also have been fine to use t0/t1. Yeah, I understand that. It was easier to rename and not confuse something. Could you please rename them during commit? Have I to send new patch version? ~ Oleksii
On 03/03/2023 10:42 am, Oleksii wrote: > On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote: >> On 03/03/2023 10:24 am, Oleksii Kurochko wrote: >>> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> >> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> >> >>> diff --git a/xen/arch/riscv/riscv64/head.S >>> b/xen/arch/riscv/riscv64/head.S >>> index adf5d6c74a..8887f0cbd4 100644 >>> --- a/xen/arch/riscv/riscv64/head.S >>> +++ b/xen/arch/riscv/riscv64/head.S >>> @@ -18,6 +19,14 @@ ENTRY(start) >>> li t0, SSTATUS_FS >>> csrc CSR_SSTATUS, t0 >>> >>> + /* Clear the BSS */ >>> + la t3, __bss_start >>> + la t4, __bss_end >>> +.L_clear_bss: >>> + REG_S zero, (t3) >>> + add t3, t3, __SIZEOF_POINTER__ >>> + bltu t3, t4, .L_clear_bss >> Using t3/t4 is fine, but it would also have been fine to use t0/t1. > Yeah, I understand that. It was easier to rename and not confuse > something. > > Could you please rename them during commit? > Have I to send new patch version? No need to send another patch. TBH, I wasn't intending to change it at all - this was just supposed to be a note - but I can if you'd prefer. ~Andrew
On Fri, 2023-03-03 at 10:53 +0000, Andrew Cooper wrote: > On 03/03/2023 10:42 am, Oleksii wrote: > > On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote: > > > On 03/03/2023 10:24 am, Oleksii Kurochko wrote: > > > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> > > > > > > > diff --git a/xen/arch/riscv/riscv64/head.S > > > > b/xen/arch/riscv/riscv64/head.S > > > > index adf5d6c74a..8887f0cbd4 100644 > > > > --- a/xen/arch/riscv/riscv64/head.S > > > > +++ b/xen/arch/riscv/riscv64/head.S > > > > @@ -18,6 +19,14 @@ ENTRY(start) > > > > li t0, SSTATUS_FS > > > > csrc CSR_SSTATUS, t0 > > > > > > > > + /* Clear the BSS */ > > > > + la t3, __bss_start > > > > + la t4, __bss_end > > > > +.L_clear_bss: > > > > + REG_S zero, (t3) > > > > + add t3, t3, __SIZEOF_POINTER__ > > > > + bltu t3, t4, .L_clear_bss > > > Using t3/t4 is fine, but it would also have been fine to use > > > t0/t1. > > Yeah, I understand that. It was easier to rename and not confuse > > something. > > > > Could you please rename them during commit? > > Have I to send new patch version? > > No need to send another patch. TBH, I wasn't intending to change it > at > all - this was just supposed to be a note - but I can if you'd > prefer. Feel free to do that. Thanks. ~ Oleksii
On Fri, Mar 03, 2023 at 12:24:24PM +0200, Oleksii Kurochko wrote: > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > --- > xen/arch/riscv/riscv64/head.S | 9 +++++++++ > xen/arch/riscv/setup.c | 8 ++++++++ > 2 files changed, 17 insertions(+) > > diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S > index adf5d6c74a..8887f0cbd4 100644 > --- a/xen/arch/riscv/riscv64/head.S > +++ b/xen/arch/riscv/riscv64/head.S > @@ -1,3 +1,4 @@ > +#include <asm/asm.h> > #include <asm/riscv_encoding.h> > > .section .text.header, "ax", %progbits > @@ -18,6 +19,14 @@ ENTRY(start) > li t0, SSTATUS_FS > csrc CSR_SSTATUS, t0 > > + /* Clear the BSS */ > + la t3, __bss_start > + la t4, __bss_end > +.L_clear_bss: > + REG_S zero, (t3) > + add t3, t3, __SIZEOF_POINTER__ > + bltu t3, t4, .L_clear_bss > + > la sp, cpu0_boot_stack > li t0, STACK_SIZE > add sp, sp, t0 > diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c > index d9723fe1c0..929565720b 100644 > --- a/xen/arch/riscv/setup.c > +++ b/xen/arch/riscv/setup.c > @@ -7,6 +7,14 @@ > unsigned char __initdata cpu0_boot_stack[STACK_SIZE] > __aligned(STACK_SIZE); > > +/* > + * To be sure that .bss isn't zero. It will simplify code of > + * .bss initialization. > + * TODO: > + * To be deleted when the first real .bss user appears > + */ > +int dummy_bss __attribute__((unused)); > + > void __init noreturn start_xen(unsigned long bootcpu_id, > unsigned long dtb_base) > { > -- > 2.39.0 > > Reviewed-by: Bobby Eshleman <bobbyeshleman@gmail.com>
diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index adf5d6c74a..8887f0cbd4 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -1,3 +1,4 @@ +#include <asm/asm.h> #include <asm/riscv_encoding.h> .section .text.header, "ax", %progbits @@ -18,6 +19,14 @@ ENTRY(start) li t0, SSTATUS_FS csrc CSR_SSTATUS, t0 + /* Clear the BSS */ + la t3, __bss_start + la t4, __bss_end +.L_clear_bss: + REG_S zero, (t3) + add t3, t3, __SIZEOF_POINTER__ + bltu t3, t4, .L_clear_bss + la sp, cpu0_boot_stack li t0, STACK_SIZE add sp, sp, t0 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index d9723fe1c0..929565720b 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -7,6 +7,14 @@ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); +/* + * To be sure that .bss isn't zero. It will simplify code of + * .bss initialization. + * TODO: + * To be deleted when the first real .bss user appears + */ +int dummy_bss __attribute__((unused)); + void __init noreturn start_xen(unsigned long bootcpu_id, unsigned long dtb_base) {
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- xen/arch/riscv/riscv64/head.S | 9 +++++++++ xen/arch/riscv/setup.c | 8 ++++++++ 2 files changed, 17 insertions(+)