From patchwork Tue May 31 02:54:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 9143173 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8760860754 for ; Tue, 31 May 2016 02:56:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 805582198E for ; Tue, 31 May 2016 02:56:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 74CBE2819C; Tue, 31 May 2016 02:56:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 26D472198E for ; Tue, 31 May 2016 02:56:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b7ZpN-0000Xc-I9; Tue, 31 May 2016 02:54:45 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b7ZpM-0000Ws-09 for xen-devel@lists.xen.org; Tue, 31 May 2016 02:54:44 +0000 Received: from [85.158.139.211] by server-7.bemta-5.messagelabs.com id BB/60-14119-3FCFC475; Tue, 31 May 2016 02:54:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRWlGSWpSXmKPExsVyMfSOnu6nPz7 hBme61C2WfFzM4sDocXT3b6YAxijWzLyk/IoE1ow1C1ezFDwRqHgzfQprA+NF3i5GLg4hgYmM Ere/TGTuYuTkYBGYxywx6Z0BSEJCoJ9VYt7UFSwgCQmBGIkj+09A2RUSba/vs3UxcgB1K0l0T KiAGPSbUeLMnT2sIDVsAioS39/0s0LUm0mcPzmTCcQWEZCWuPb5MiOIzSyQKXHjy0R2kDnCAs ESbUtMIG5QlZjQNwmslVfAQmLDp5eMEGOUJF5dOQZ2AqeApcSvtoPsILYQUM3r6e/YJzAKLmB kWMWoXpxaVJZapGuhl1SUmZ5RkpuYmaNraGCql5taXJyYnpqTmFSsl5yfu4kRGGwMQLCD8WCz 8yFGSQ4mJVFeq98+4UJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkeFmBwSskWJSanlqRlpkDDHuYt AQHj5II72OQVt7igsTc4sx0iNQpRmOOLb+vrWXi2Db13lomIZa8/LxUKXHeVyClAiClGaV5cI Ng8XiJUVZKmJcR6DQhnoLUotzMElT5V4ziHIxKwrzPQKbwZOaVwO17BXQKE9Ap8Rlgp5QkIqS kGhglFdbb3gzPOHv8+RLdFO5rdcer21+zxnVE1whdkFYKUHzrlfzKR4Mj/hHT5JbXDcbSU3il s1535DWmM6jtVmiKLYndMO1Dl9nnW5bzS2M/hna+2FV2t2e78jWjhxMPtt7dnPro7qwJlQcE1 MWfrWY8WMRyP8/T6efpmT95VBdaXFXILN0yd6ISS3FGoqEWc1FxIgBqT2yGwgIAAA== X-Env-Sender: wei.chen@linaro.org X-Msg-Ref: server-4.tower-206.messagelabs.com!1464663281!42378876!1 X-Originating-IP: [209.85.220.46] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36700 invoked from network); 31 May 2016 02:54:42 -0000 Received: from mail-pa0-f46.google.com (HELO mail-pa0-f46.google.com) (209.85.220.46) by server-4.tower-206.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 31 May 2016 02:54:42 -0000 Received: by mail-pa0-f46.google.com with SMTP id bz2so36935884pad.1 for ; Mon, 30 May 2016 19:54:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0qVVjQN6F9HJ2/ur8h67pxd1TGxUcUMlciktF/HLxj0=; b=WpxrFqk783zYUX8e7bblm2abPKXdVIfKvYWI1sKR2keEJVYWYVb8XpDSqsU2KtUdgq qU5AEP5pADREubUztwzBd3+d8nICsTiTdxUzVbPOhm3iW0XQ3mLk4sAJ20OTpcA9XT5Q RknurkYyzwqPKtyOHPskBOwToqGoj15/zOnLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0qVVjQN6F9HJ2/ur8h67pxd1TGxUcUMlciktF/HLxj0=; b=JRkFBkXaY78CVmc02DZehv0vd1IPE8KBf0TOGp5p8iirXpkWnaUdlFM+oIwxiw1EgO 1pqMb4sf+psfIC/glC6GciZk+3HWWLYsSR9+3zR3kgyD9y5csebdpEsXESqISYzlg5SQ 2JhGf3QXkohjIAJxp/41fDjPgw+SAMcOr08J0mKpTnhhnP6kBEIQGiE2rznJxDtGv9/9 rhTbLEwkjfI/cNw6qb3c/zSxGkqadbP41d4XNs1IkeM2nPRG78Oq08m2OFR6Np6dSKNw KcREcmMyP2twUVD0ATlxJWDIhAxxWVQky+RksZoMeXRbaZaJGVJElCxIs9SVrN4nlttv ohfw== X-Gm-Message-State: ALyK8tKEf+vo3r3fKPSwQvCiFkUAPOL9r5LBJqX2ZKp0i07SUH1AdtRZ8RGOa3m/LHWRulaD X-Received: by 10.66.81.193 with SMTP id c1mr51038848pay.33.1464663281101; Mon, 30 May 2016 19:54:41 -0700 (PDT) Received: from localhost.members.linode.com ([2400:8900::f03c:91ff:fe56:1324]) by smtp.gmail.com with ESMTPSA id n190sm35879825pfn.23.2016.05.30.19.54.39 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 May 2016 19:54:40 -0700 (PDT) From: Wei Chen X-Google-Original-From: Wei Chen To: xen-devel@lists.xen.org Date: Tue, 31 May 2016 10:54:13 +0800 Message-Id: <20160531025414.15539-4-Wei.Chen@linaro.org> X-Mailer: git-send-email 2.9.0.rc0 In-Reply-To: <20160531025414.15539-1-Wei.Chen@linaro.org> References: <20160531025414.15539-1-Wei.Chen@linaro.org> Cc: julien.grall@arm.com, sstabellini@kernel.org, Wei Chen , steve.capper@arm.com Subject: [Xen-devel] [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, MPIDR_HWID_MASK is using the bit definition of AArch32 MPIDR register. But from D7.2.67 of ARM ARM (DDI 0487A.i) we can see there are 4 levels of affinity on AArch64 whilst AArch32 has only 3. So, this value is not correct when Xen is running on AArch64. Now, we use the value 0xff00ffffff for this macro on AArch64. But neither of this value and its bitwise invert value can be used in mov instruction with the encoding of {imm16:shift} or {imms:immr}. So we have to use ldr to load the bitwise invert value to register. The details of mov immediate encoding are listed in C4.2.5 of ARM ARM (DDI 0487A.i). Signed-off-by: Wei Chen Reviewed-by: Julien Grall --- v3-->v4: 1. Update version number. v2-->v3: 1. Add version information of mentioned ARM ARM. v1-->v2: Address Julien's comments 1. Fix typos in commit messages. 2. Explain valid MPIDR_HWID_MASK value in AArch64. 3. Simply explain mov immediate encoding. --- xen/arch/arm/arm64/head.S | 2 +- xen/include/asm-arm/processor.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index d5831f2..3090beb 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -270,7 +270,7 @@ common_start: tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */ tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */ - mov x13, #(~MPIDR_HWID_MASK) + ldr x13, =(~MPIDR_HWID_MASK) bic x24, x0, x13 /* Mask out flags to get CPU ID */ 1: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b4cce7e..284ad6a 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -18,7 +18,11 @@ #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) +#ifdef CONFIG_ARM_64 +#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) +#else #define MPIDR_HWID_MASK _AC(0xffffff,U) +#endif #define MPIDR_INVALID (~MPIDR_HWID_MASK) #define MPIDR_LEVEL_BITS (8)