From patchwork Sun Aug 14 20:37:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 9280085 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5540360231 for ; Sun, 14 Aug 2016 20:47:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 465C7289A7 for ; Sun, 14 Aug 2016 20:47:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3ADBF28A1A; Sun, 14 Aug 2016 20:47:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 866C1289A7 for ; Sun, 14 Aug 2016 20:47:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bZ2Gm-00004t-QH; Sun, 14 Aug 2016 20:44:32 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bZ2Gl-0008Vx-IV for xen-devel@lists.xenproject.org; Sun, 14 Aug 2016 20:44:31 +0000 Received: from [85.158.143.35] by server-7.bemta-6.messagelabs.com id A6/77-15404-E28D0B75; Sun, 14 Aug 2016 20:44:30 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeJIrShJLcpLzFFi42LpubySR1fvxoZ wg22ruCy+b5nM5MDocfjDFZYAxijWzLyk/IoE1oz1Gx6wFZzUr2iYM5O9gfGfWhcjF4eQwDZG iZc3lzB3MXJwsAmYSsz4r9LFyMkhIqAgsbn3GStIDbPAU1aJPxM2MYEkhAUCJXp3T2EFsVkEV CUmr/7FDmLzClhJbLv9kBnElhCQk7i07QuYzSlgLTHzXitYrxBQzdXDfWBxUQExic1tu1gheg UlTs58wgJyA7OAusT6eUITGHlnIcnMQsgsYGRaxahenFpUllqka6KXVJSZnlGSm5iZo2toYKa Xm1pcnJiempOYVKyXnJ+7iREYOAxAsIOx+7L/IUZJDiYlUV4d83XhQnxJ+SmVGYnFGfFFpTmp xYcYZTg4lCR4T13bEC4kWJSanlqRlpkDDGGYtAQHj5II73OQNG9xQWJucWY6ROoUo6KUOO8jk IQASCKjNA+uDRY3lxhlpYR5GYEOEeIpSC3KzSxBlX/FKM7BqCTM+w5kCk9mXgnc9FdAi5mAFu tLgy0uSURISTUwCjh+WljZef12whbDHU+2XUjYJX6K4Zfp/HarvV0WfJxO2y3YzV8rcH/RZzH uOHt8lRTD7u1iWUl6fcGfDoQxPSnzuRyzxGFL7vfLKcsSvlYrW214WVBVzn/o6fzePdkrd5jX x4l/9U27EZE703XRj9BiqYgFf7S7hR78zL8+6UO53/Qf1uKvlViKMxINtZiLihMB5p8rK5YCA AA= X-Env-Sender: gregkh@linuxfoundation.org X-Msg-Ref: server-10.tower-21.messagelabs.com!1471207468!28320261!1 X-Originating-IP: [140.211.169.12] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6856 invoked from network); 14 Aug 2016 20:44:29 -0000 Received: from mail.linuxfoundation.org (HELO mail.linuxfoundation.org) (140.211.169.12) by server-10.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 14 Aug 2016 20:44:29 -0000 Received: from localhost (pes75-3-78-192-101-3.fbxo.proxad.net [78.192.101.3]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 41126725; Sun, 14 Aug 2016 20:44:27 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Date: Sun, 14 Aug 2016 22:37:27 +0200 Message-Id: <20160814202505.879138924@linuxfoundation.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160814202504.908694181@linuxfoundation.org> References: <20160814202504.908694181@linuxfoundation.org> User-Agent: quilt/0.64 MIME-Version: 1.0 Cc: Juergen Gross , Denys Vlasenko , xen-devel@lists.xenproject.org, Toshi Kani , Peter Zijlstra , Greg Kroah-Hartman , "Luis R. Rodriguez" , "H. Peter Anvin" , stable@vger.kernel.org, Andy Lutomirski , paul.gortmaker@windriver.com, Ingo Molnar , Borislav Petkov , Brian Gerst , Toshi Kani , Andrew Morton , Borislav Petkov , Linus Torvalds , Thomas Gleixner , elliott@hpe.com Subject: [Xen-devel] [PATCH 4.6 23/56] x86/mm/pat: Add support of non-default PAT MSR setting X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP 4.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Toshi Kani commit 02f037d641dc6672be5cfe7875a48ab99b95b154 upstream. In preparation for fixing a regression caused by: 9cd25aac1f44 ("x86/mm/pat: Emulate PAT when it is disabled")' ... PAT needs to support a case that PAT MSR is initialized with a non-default value. When pat_init() is called and PAT is disabled, it initializes the PAT table with the BIOS default value. Xen, however, sets PAT MSR with a non-default value to enable WC. This causes inconsistency between the PAT table and PAT MSR when PAT is set to disable on Xen. Change pat_init() to handle the PAT disable cases properly. Add init_cache_modes() to handle two cases when PAT is set to disable. 1. CPU supports PAT: Set PAT table to be consistent with PAT MSR. 2. CPU does not support PAT: Set PAT table to be consistent with PWT and PCD bits in a PTE. Note, __init_cache_modes(), renamed from pat_init_cache_modes(), will be changed to a static function in a later patch. Signed-off-by: Toshi Kani Reviewed-by: Thomas Gleixner Cc: Andrew Morton Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Juergen Gross Cc: Linus Torvalds Cc: Luis R. Rodriguez Cc: Peter Zijlstra Cc: Toshi Kani Cc: elliott@hpe.com Cc: konrad.wilk@oracle.com Cc: paul.gortmaker@windriver.com Cc: xen-devel@lists.xenproject.org Link: http://lkml.kernel.org/r/1458769323-24491-2-git-send-email-toshi.kani@hpe.com Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/pat.h | 2 - arch/x86/mm/pat.c | 73 ++++++++++++++++++++++++++++++++------------- arch/x86/xen/enlighten.c | 2 - 3 files changed, 55 insertions(+), 22 deletions(-) --- a/arch/x86/include/asm/pat.h +++ b/arch/x86/include/asm/pat.h @@ -6,7 +6,7 @@ bool pat_enabled(void); extern void pat_init(void); -void pat_init_cache_modes(u64); +void __init_cache_modes(u64); extern int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm); --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -181,7 +181,7 @@ static enum page_cache_mode pat_get_cach * configuration. * Using lower indices is preferred, so we start with highest index. */ -void pat_init_cache_modes(u64 pat) +void __init_cache_modes(u64 pat) { enum page_cache_mode cache; char pat_msg[33]; @@ -207,9 +207,6 @@ static void pat_bsp_init(u64 pat) return; } - if (!pat_enabled()) - goto done; - rdmsrl(MSR_IA32_CR_PAT, tmp_pat); if (!tmp_pat) { pat_disable("PAT MSR is 0, disabled."); @@ -218,15 +215,11 @@ static void pat_bsp_init(u64 pat) wrmsrl(MSR_IA32_CR_PAT, pat); -done: - pat_init_cache_modes(pat); + __init_cache_modes(pat); } static void pat_ap_init(u64 pat) { - if (!pat_enabled()) - return; - if (!cpu_has_pat) { /* * If this happens we are on a secondary CPU, but switched to @@ -238,18 +231,32 @@ static void pat_ap_init(u64 pat) wrmsrl(MSR_IA32_CR_PAT, pat); } -void pat_init(void) +static void init_cache_modes(void) { - u64 pat; - struct cpuinfo_x86 *c = &boot_cpu_data; + u64 pat = 0; + static int init_cm_done; - if (!pat_enabled()) { + if (init_cm_done) + return; + + if (boot_cpu_has(X86_FEATURE_PAT)) { + /* + * CPU supports PAT. Set PAT table to be consistent with + * PAT MSR. This case supports "nopat" boot option, and + * virtual machine environments which support PAT without + * MTRRs. In specific, Xen has unique setup to PAT MSR. + * + * If PAT MSR returns 0, it is considered invalid and emulates + * as No PAT. + */ + rdmsrl(MSR_IA32_CR_PAT, pat); + } + + if (!pat) { /* * No PAT. Emulate the PAT table that corresponds to the two - * cache bits, PWT (Write Through) and PCD (Cache Disable). This - * setup is the same as the BIOS default setup when the system - * has PAT but the "nopat" boot option has been specified. This - * emulated PAT table is used when MSR_IA32_CR_PAT returns 0. + * cache bits, PWT (Write Through) and PCD (Cache Disable). + * This setup is also the same as the BIOS default setup. * * PTE encoding: * @@ -266,10 +273,36 @@ void pat_init(void) */ pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) | PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC); + } + + __init_cache_modes(pat); + + init_cm_done = 1; +} + +/** + * pat_init - Initialize PAT MSR and PAT table + * + * This function initializes PAT MSR and PAT table with an OS-defined value + * to enable additional cache attributes, WC and WT. + * + * This function must be called on all CPUs using the specific sequence of + * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this + * procedure for PAT. + */ +void pat_init(void) +{ + u64 pat; + struct cpuinfo_x86 *c = &boot_cpu_data; + + if (!pat_enabled()) { + init_cache_modes(); + return; + } - } else if ((c->x86_vendor == X86_VENDOR_INTEL) && - (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || - ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { + if ((c->x86_vendor == X86_VENDOR_INTEL) && + (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || + ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { /* * PAT support with the lower four entries. Intel Pentium 2, * 3, M, and 4 are affected by PAT errata, which makes the --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -1623,7 +1623,7 @@ asmlinkage __visible void __init xen_sta * configuration. */ rdmsrl(MSR_IA32_CR_PAT, pat); - pat_init_cache_modes(pat); + __init_cache_modes(pat); /* keep using Xen gdt for now; no urgent need to change it */