From patchwork Fri Feb 17 06:39:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9578889 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9AB79600C5 for ; Fri, 17 Feb 2017 06:43:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BAD5286A1 for ; Fri, 17 Feb 2017 06:43:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80A15286A9; Fri, 17 Feb 2017 06:43:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 04E4B286A1 for ; Fri, 17 Feb 2017 06:43:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecE0-0002cn-RC; Fri, 17 Feb 2017 06:41:00 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecDz-0002bZ-QF for xen-devel@lists.xen.org; Fri, 17 Feb 2017 06:40:59 +0000 Received: from [193.109.254.147] by server-9.bemta-6.messagelabs.com id BE/C0-27165-BFA96A85; Fri, 17 Feb 2017 06:40:59 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRWlGSWpSXmKPExsVywNykWPfXrGU RBl8fiVgs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnrLpxlLPhlWDHztkAD4wH1LkYuDiGBaYwS e6dcZeli5OSQEOCVOLJsBmsXIweQ7Sfx4roFRE0vo8ShtbtYQWrYBPQlVjw+CGaLCEhLXPt8m RGkiFngLKPEkrsNTCAJYQFjibnXj4HZLAKqEi+ebGIGsXkF7CSOHfoCtUxe4sLVU2A2J1D8z8 MP7CC2kICtxPtP95gnMPIuYGRYxahenFpUllqka6KXVJSZnlGSm5iZo2toYKaXm1pcnJiempO YVKyXnJ+7iREYDAxAsIOx+7L/IUZJDiYlUd5F05ZFCPEl5adUZiQWZ8QXleakFh9ilOHgUJLg 5QYGl5BgUWp6akVaZg4wLGHSEhw8SiK8HCBp3uKCxNzizHSI1ClGRSlx3hszgRICIImM0jy4N lgsXGKUlRLmZQQ6RIinILUoN7MEVf4VozgHo5Iw7wWQKTyZeSVw018BLWYCWtwZsRRkcUkiQk qqgTHc/s7napH15XeKLglebg//7y6/qXjttccnr+7dlZfJ5zbJo8gk7l5X7tWDJ2f6a98In3b ks7KM96+gLdlzs7vO5E2s3z4hUPvMFa3z2/hu8MyZctMzu7WAjYPzSLHzTpeWrRGKf28/Zv/+ Nyt77ufglYULDhWXWZ7yXL3m5r9r62p6ps/jO3FHiaU4I9FQi7moOBEAy8Wd5YACAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1487313633!34675007!12 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33511 invoked from network); 17 Feb 2017 06:40:57 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-15.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Feb 2017 06:40:57 -0000 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Feb 2017 22:40:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="65781556" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.133]) by orsmga005.jf.intel.com with ESMTP; 16 Feb 2017 22:40:56 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Feb 2017 14:39:29 +0800 Message-Id: <20170217063936.13208-13-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170217063936.13208-1-haozhong.zhang@intel.com> References: <20170217063936.13208-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Christoph Egger , Andrew Cooper , Jan Beulich , Liu Jinsong Subject: [Xen-devel] [PATCH 12/19] x86/mce: handle LMCE locally X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP LMCE is sent to only one CPU thread, so MCE handler, barriers and softirq handler should go without waiting for other CPUs, when handling LMCE. Note LMCE is still broadcast to all vcpus as regular MCE on Intel CPU right now. Signed-off-by: Haozhong Zhang --- Cc: Christoph Egger Cc: Liu Jinsong Cc: Jan Beulich Cc: Andrew Cooper --- xen/arch/x86/cpu/mcheck/barrier.c | 4 ++-- xen/arch/x86/cpu/mcheck/mcaction.c | 4 +++- xen/arch/x86/cpu/mcheck/mce.c | 25 ++++++++++++++++++++++--- xen/arch/x86/cpu/mcheck/mce.h | 3 +++ xen/arch/x86/cpu/mcheck/x86_mca.h | 4 +++- 5 files changed, 33 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/barrier.c b/xen/arch/x86/cpu/mcheck/barrier.c index 5dce1fb..869fd20 100644 --- a/xen/arch/x86/cpu/mcheck/barrier.c +++ b/xen/arch/x86/cpu/mcheck/barrier.c @@ -20,7 +20,7 @@ void mce_barrier_enter(struct mce_softirq_barrier *bar) { int gen; - if (!mce_broadcast) + if ( !mce_broadcast || __get_cpu_var(lmce_in_process) ) return; atomic_inc(&bar->ingen); gen = atomic_read(&bar->outgen); @@ -38,7 +38,7 @@ void mce_barrier_exit(struct mce_softirq_barrier *bar) { int gen; - if ( !mce_broadcast ) + if ( !mce_broadcast || __get_cpu_var(lmce_in_process) ) return; atomic_inc(&bar->outgen); gen = atomic_read(&bar->ingen); diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/mcaction.c index 8b2b834..90c68ff 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.c +++ b/xen/arch/x86/cpu/mcheck/mcaction.c @@ -95,7 +95,9 @@ mc_memerr_dhandler(struct mca_binfo *binfo, bank->mc_addr = gfn << PAGE_SHIFT | (bank->mc_addr & (PAGE_SIZE -1 )); - if ( fill_vmsr_data(bank, d, global->mc_gstatus, + /* TODO: support injecting LMCE */ + if ( fill_vmsr_data(bank, d, + global->mc_gstatus & ~MCG_STATUS_LMCE, vmce_vcpuid == VMCE_INJECT_BROADCAST) == -1 ) { mce_printk(MCE_QUIET, "Fill vMCE# data for DOM%d " diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 95a9da3..2d69222 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -42,6 +42,17 @@ DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, poll_bankmask); DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, no_cmci_banks); DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_clear_banks); +/* + * Flag to indicate whether the current MCE on this CPU is a LMCE. + * + * The MCE handler should set/clear this flag before entering any MCE + * barriers and raising MCE softirq. MCE barriers rely on this flag to + * decide whether they need to wait for other CPUs. MCE softirq handler + * relies on this flag to decide whether it needs to handle pending + * MCEs on other CPUs. + */ +DEFINE_PER_CPU(bool, lmce_in_process); + static void intpose_init(void); static void mcinfo_clear(struct mc_info *); struct mca_banks *mca_allbanks; @@ -399,6 +410,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask, sp->errcnt = errcnt; sp->ripv = (gstatus & MCG_STATUS_RIPV) != 0; sp->eipv = (gstatus & MCG_STATUS_EIPV) != 0; + sp->lmce = (gstatus & MCG_STATUS_LMCE) != 0; sp->uc = uc; sp->pcc = pcc; sp->recoverable = recover; @@ -462,6 +474,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs) uint64_t gstatus; mctelem_cookie_t mctc = NULL; struct mca_summary bs; + bool *lmce_in_process = &__get_cpu_var(lmce_in_process); mce_spin_lock(&mce_logout_lock); @@ -505,6 +518,8 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs) } mce_spin_unlock(&mce_logout_lock); + *lmce_in_process = bs.lmce; + mce_barrier_enter(&mce_trap_bar); if ( mctc != NULL && mce_urgent_action(regs, mctc)) cpumask_set_cpu(smp_processor_id(), &mce_fatal_cpus); @@ -1709,6 +1724,7 @@ static void mce_softirq(void) { int cpu = smp_processor_id(); unsigned int workcpu; + bool lmce = per_cpu(lmce_in_process, cpu); mce_printk(MCE_VERBOSE, "CPU%d enter softirq\n", cpu); @@ -1738,9 +1754,12 @@ static void mce_softirq(void) /* Step1: Fill DOM0 LOG buffer, vMCE injection buffer and * vMCE MSRs virtualization buffer */ - for_each_online_cpu(workcpu) { - mctelem_process_deferred(workcpu, mce_delayed_action); - } + if ( lmce ) + mctelem_process_deferred(cpu, mce_delayed_action); + else + for_each_online_cpu(workcpu) { + mctelem_process_deferred(workcpu, mce_delayed_action); + } /* Step2: Send Log to DOM0 through vIRQ */ if (dom0_vmce_enabled()) { diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 2f4e7a4..2c033af 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -110,12 +110,15 @@ struct mca_summary { bool_t uc; /* UC flag */ bool_t pcc; /* PCC flag */ bool_t recoverable; /* software error recoverable flag */ + bool_t lmce; /* LMCE flag (Intel specific) */ }; DECLARE_PER_CPU(struct mca_banks *, poll_bankmask); DECLARE_PER_CPU(struct mca_banks *, no_cmci_banks); DECLARE_PER_CPU(struct mca_banks *, mce_clear_banks); +DECLARE_PER_CPU(bool, lmce_in_process); + extern bool_t cmci_support; extern bool_t is_mc_panic; extern bool_t mce_broadcast; diff --git a/xen/arch/x86/cpu/mcheck/x86_mca.h b/xen/arch/x86/cpu/mcheck/x86_mca.h index e25d619..322b7d4 100644 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h @@ -42,7 +42,9 @@ #define MCG_STATUS_RIPV 0x0000000000000001ULL #define MCG_STATUS_EIPV 0x0000000000000002ULL #define MCG_STATUS_MCIP 0x0000000000000004ULL -/* Bits 3-63 are reserved */ +#define MCG_STATUS_LMCE 0x0000000000000008ULL /* Intel specific */ +/* Bits 3-63 are reserved on CPU not supporting LMCE */ +/* Bits 4-63 are reserved on CPU supporting LMCE */ /* Bitfield of MSR_K8_MCi_STATUS registers */ /* MCA error code */