From patchwork Fri Feb 17 06:39:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9578893 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8F98E600C5 for ; Fri, 17 Feb 2017 06:43:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 809A5286A1 for ; Fri, 17 Feb 2017 06:43:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75816286A7; Fri, 17 Feb 2017 06:43:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0328C286A1 for ; Fri, 17 Feb 2017 06:43:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecE3-0002f6-2k; Fri, 17 Feb 2017 06:41:03 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecE1-0002dU-JF for xen-devel@lists.xen.org; Fri, 17 Feb 2017 06:41:01 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id 34/63-25093-DFA96A85; Fri, 17 Feb 2017 06:41:01 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRWlGSWpSXmKPExsVywNykWPfPrGU RBp/bRSyWfFzM4sDocXT3b6YAxijWzLyk/IoE1oy2b5NYC2boVJz4vpW1gfGgUhcjJ4eQwDRG iUUnK0FsCQFeiSPLZrBC2H4SOybPY+xi5AKq6WWUaOqbyAySYBPQl1jx+CBYkYiAtMS1z5fBi pgFzjJKLLnbwNTFyMEhLOAlMftHNUgNi4CqxIW+2ywgNq+AncTOD9fYIBbIS1y4egoszgkU// PwAzvEQbYS7z/dY57AyLuAkWEVo3pxalFZapGuiV5SUWZ6RkluYmaOrqGBmV5uanFxYnpqTmJ SsV5yfu4mRmAwMADBDsbuy/6HGCU5mJREeRdNWxYhxJeUn1KZkVicEV9UmpNafIhRhoNDSYKX GxhcQoJFqempFWmZOcCwhElLcPAoifBygKR5iwsSc4sz0yFSpxgVpcR5b8wESgiAJDJK8+DaY LFwiVFWSpiXEegQIZ6C1KLczBJU+VeM4hyMSsK8F0Cm8GTmlcBNfwW0mAlocWfEUpDFJYkIKa kGxlVrozUncgZOSuvek3H8j64U95ui3vsV6ocLClYa7zZOWMz7OmOGzxNPnnqDpnfzni828BM +kn9qo9vH9JmH5LTn++5uYl0/55mHRX550i+Fq3qOhon/bzn2yCjUTVjGUGm0Y5XIxglTJvo4 3X2faux7S7vKpv/Gg9y7fbPWRmSbWzhePWPtrcRSnJFoqMVcVJwIACM3z82AAgAA X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1487313633!34675007!13 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33608 invoked from network); 17 Feb 2017 06:40:59 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-15.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Feb 2017 06:40:59 -0000 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Feb 2017 22:40:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="65781563" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.133]) by orsmga005.jf.intel.com with ESMTP; 16 Feb 2017 22:40:58 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Feb 2017 14:39:30 +0800 Message-Id: <20170217063936.13208-14-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170217063936.13208-1-haozhong.zhang@intel.com> References: <20170217063936.13208-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Christoph Egger , Andrew Cooper , Jan Beulich , Liu Jinsong Subject: [Xen-devel] [PATCH 13/19] x86/mce_intel: detect and enable LMCE on Intel host X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable LMCE if it's supported by the host CPU. If Xen boot parameter "mce_fb = 1" is present, LMCE will be disabled forcibly. Signed-off-by: Haozhong Zhang --- Cc: Christoph Egger Cc: Liu Jinsong Cc: Jan Beulich Cc: Andrew Cooper --- xen/arch/x86/cpu/mcheck/mce.h | 1 + xen/arch/x86/cpu/mcheck/mce_intel.c | 44 ++++++++++++++++++++++++++++++++----- xen/arch/x86/cpu/mcheck/x86_mca.h | 5 +++++ xen/include/asm-x86/msr-index.h | 2 ++ 4 files changed, 46 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 2c033af..461141a 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -38,6 +38,7 @@ enum mcheck_type { }; extern uint8_t cmci_apic_vector; +extern bool lmce_support; /* Init functions */ enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 9e5ee3d..b4cc41a 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -29,6 +29,9 @@ boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; +/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ +bool __read_mostly lmce_support = 0; + /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */ #define INTEL_MCCOD_MASK 0xFFFF @@ -677,10 +680,34 @@ static int mce_is_broadcast(struct cpuinfo_x86 *c) return 0; } +static bool intel_enable_lmce(void) +{ + uint64_t msr_content; + + /* + * Section "Enabling Local Machine Check" in Intel SDM Vol 3 + * requires software must ensure the LOCK bit and LMCE_ON bit + * of MSR_IA32_FEATURE_CONTROL are set before setting + * MSR_IA32_MCG_EXT_CTL.LMCE_EN. + */ + + if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, msr_content) ) + return 0; + + if ( msr_content & + (IA32_FEATURE_CONTROL_LOCK | IA32_FEATURE_CONTROL_LMCE_ON) ) + { + wrmsrl(MSR_IA32_MCG_EXT_CTL, MCG_EXT_CTL_LMCE_EN); + return 1; + } + + return 0; +} + /* Check and init MCA */ static void intel_init_mca(struct cpuinfo_x86 *c) { - bool_t broadcast, cmci = 0, ser = 0; + bool_t broadcast, cmci = 0, ser = 0, lmce = 0; int ext_num = 0, first; uint64_t msr_content; @@ -700,26 +727,31 @@ static void intel_init_mca(struct cpuinfo_x86 *c) first = mce_firstbank(c); + if ( !mce_force_broadcast && (msr_content & MCG_LMCE_P) ) + lmce = intel_enable_lmce(); + if (smp_processor_id() == 0) { dprintk(XENLOG_INFO, "MCA Capability: BCAST %x SER %x" - " CMCI %x firstbank %x extended MCE MSR %x\n", - broadcast, ser, cmci, first, ext_num); + " CMCI %x firstbank %x extended MCE MSR %x LMCE %x\n", + broadcast, ser, cmci, first, ext_num, lmce); mce_broadcast = broadcast; cmci_support = cmci; ser_support = ser; nr_intel_ext_msrs = ext_num; firstbank = first; + lmce_support = lmce; } else if (cmci != cmci_support || ser != ser_support || broadcast != mce_broadcast || - first != firstbank || ext_num != nr_intel_ext_msrs) + first != firstbank || ext_num != nr_intel_ext_msrs || + lmce != lmce_support) { dprintk(XENLOG_WARNING, - "CPU %u has different MCA capability (%x,%x,%x,%x,%x)" + "CPU %u has different MCA capability (%x,%x,%x,%x,%x,%x)" " than BSP, may cause undetermined result!!!\n", - smp_processor_id(), broadcast, ser, cmci, first, ext_num); + smp_processor_id(), broadcast, ser, cmci, first, ext_num, lmce); } } diff --git a/xen/arch/x86/cpu/mcheck/x86_mca.h b/xen/arch/x86/cpu/mcheck/x86_mca.h index 322b7d4..3b5060e 100644 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h @@ -36,6 +36,7 @@ #define MCG_TES_P (1ULL<<11) /* Intel specific */ #define MCG_EXT_CNT 16 /* Intel specific */ #define MCG_SER_P (1ULL<<24) /* Intel specific */ +#define MCG_LMCE_P (1ULL<<27) /* Intel specific */ /* Other bits are reserved */ /* Bitfield of the MSR_IA32_MCG_STATUS register */ @@ -46,6 +47,10 @@ /* Bits 3-63 are reserved on CPU not supporting LMCE */ /* Bits 4-63 are reserved on CPU supporting LMCE */ +/* Bitfield of MSR_IA32_MCG_EXT_CTL register (Intel Specific) */ +#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) +/* Other bits are reserved */ + /* Bitfield of MSR_K8_MCi_STATUS registers */ /* MCA error code */ #define MCi_STATUS_MCA 0x000000000000ffffULL diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 98dbff1..f0bc574 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -51,6 +51,7 @@ #define MSR_IA32_MCG_CAP 0x00000179 #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_IA32_MCG_EXT_CTL 0x000004d0 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 @@ -294,6 +295,7 @@ #define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 #define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 #define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 +#define IA32_FEATURE_CONTROL_LMCE_ON 0x100000 #define MSR_IA32_TSC_ADJUST 0x0000003b