From patchwork Fri Feb 24 10:52:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9589913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8FB2E60471 for ; Fri, 24 Feb 2017 10:55:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74468287A5 for ; Fri, 24 Feb 2017 10:55:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67D7D28951; Fri, 24 Feb 2017 10:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CFF95287A5 for ; Fri, 24 Feb 2017 10:55:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1chDVP-0003vM-4m; Fri, 24 Feb 2017 10:53:43 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1chDVN-0003tW-HT for xen-devel@lists.xen.org; Fri, 24 Feb 2017 10:53:41 +0000 Received: from [85.158.137.68] by server-5.bemta-3.messagelabs.com id 3B/EB-19998-4B010B85; Fri, 24 Feb 2017 10:53:40 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRWlGSWpSXmKPExsXS1tYhortFYEO EwYRJ4hZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8aL/atZC5abVXS+WMfcwNig3sXIxSEkMI1R YvK1SYxdjJwcEgK8EkeWzWCFsP0lZmw7zAxR1Mso8f7lfrAEm4C+xIrHB8FsEQFpiWufLzOCF DELLGSU2PmrHSjBwSEsECZxbko0SA2LgKrE1K/9YAt4BWwl/s7ZwwaxQF7iwtVTLCA2p4CdxM WDq8FqhIBq1nU/YJ7AyLuAkWEVo0ZxalFZapGukYleUlFmekZJbmJmjq6hgbFebmpxcWJ6ak5 iUrFecn7uJkZgQNQzMDDuYHx13O8QoyQHk5Io7/+H6yOE+JLyUyozEosz4otKc1KLDzHKcHAo SfBG82+IEBIsSk1PrUjLzAGGJkxagoNHSYT3HUiat7ggMbc4Mx0idYpRl+NWw543TEIsefl5q VLivIIgRQIgRRmleXAjYHFyiVFWSpiXkYGBQYinILUoN7MEVf4VozgHo5IwbyXIFJ7MvBK4Ta +AjmACOsLSeS3IESWJCCmpBsbtUUId5VsMVQs7su/zBMq72ErnafEsOdX9dMPqLyYHJaa+ST4 37V1YjJIUb0pXy/d35fPiy/TNTF7uVtQw/7isvo915c6ZItxBB/r3Mtrf1DqYMUNxa3fm9peH Zr3YU+n2+ZmhA0/ks3fBCsK//k/QuteQKtN8nFvsZ5Njb6/Qlg2bUxdayCuxFGckGmoxFxUnA gCVK/3HjgIAAA== X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1487933615!86569883!3 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5561 invoked from network); 24 Feb 2017 10:53:40 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-10.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 24 Feb 2017 10:53:40 -0000 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 02:53:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,200,1484035200"; d="scan'208";a="937650287" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.133]) by orsmga003.jf.intel.com with ESMTP; 24 Feb 2017 02:53:37 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 24 Feb 2017 18:52:53 +0800 Message-Id: <20170224105256.24668-5-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170224105256.24668-1-haozhong.zhang@intel.com> References: <20170224105256.24668-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Christoph Egger , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH 4/7] x86/vmce: fill MSR_IA32_MCG_STATUS on all vcpus in broadcast case X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The current implementation only fills MC MSRs on vcpu0 and leaves MC MSRs on other vcpus empty in the broadcast case. When guest reads 0 from MSR_IA32_MCG_STATUS on vcpuN (N > 0), it may think it's not possible to recover the execution on that vcpu and then get panic, although MSR_IA32_MCG_STATUS filled on vcpu0 may imply the injected vMCE is actually recoverable. To avoid such unnecessary guest panic, set MSR_IA32_MCG_STATUS on vcpuN (N > 0) to MCG_STATUS_MCIP|MCG_STATUS_RIPV. In addition, fill_vmsr_data(mc_bank, ...) is changed to return -EINVAL rather than 0, if an invalid domain ID is contained in mc_bank. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich --- Cc: Christoph Egger Cc: Jan Beulich Cc: Andrew Cooper Changes: * Fix the return value check of fill_vmsr_data() in mc_memerr_dhandler(). * Include the behavior change in the commit message. * Compare by vcpu id rather than vcpu structure in fill_vmsr_data() * Exlpain vMCEs injected to each vCPU in the code comment. * Update MC MSRs for *all* vCPUs and return the last error (if any). * Remove "goto" in fill_vmsr_data(). --- xen/arch/x86/cpu/mcheck/mcaction.c | 16 ++++----- xen/arch/x86/cpu/mcheck/vmce.c | 74 ++++++++++++++++++++++++++------------ xen/arch/x86/cpu/mcheck/vmce.h | 2 +- 3 files changed, 60 insertions(+), 32 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/mcaction.c index 32056f2..dab9eac 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.c +++ b/xen/arch/x86/cpu/mcheck/mcaction.c @@ -88,22 +88,22 @@ mc_memerr_dhandler(struct mca_binfo *binfo, goto vmce_failed; } + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || + global->mc_vcpuid == XEN_MC_VCPUID_INVALID) + vmce_vcpuid = VMCE_INJECT_BROADCAST; + else + vmce_vcpuid = global->mc_vcpuid; + bank->mc_addr = gfn << PAGE_SHIFT | (bank->mc_addr & (PAGE_SIZE -1 )); - if ( fill_vmsr_data(bank, d, - global->mc_gstatus) == -1 ) + if (fill_vmsr_data(bank, d, global->mc_gstatus, + vmce_vcpuid == VMCE_INJECT_BROADCAST)) { mce_printk(MCE_QUIET, "Fill vMCE# data for DOM%d " "failed\n", bank->mc_domid); goto vmce_failed; } - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || - global->mc_vcpuid == XEN_MC_VCPUID_INVALID) - vmce_vcpuid = VMCE_INJECT_BROADCAST; - else - vmce_vcpuid = global->mc_vcpuid; - /* We will inject vMCE to DOMU*/ if ( inject_vmce(d, vmce_vcpuid) < 0 ) { diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 13b692c..2caccae 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -381,38 +381,66 @@ int inject_vmce(struct domain *d, int vcpu) return ret; } -int fill_vmsr_data(struct mcinfo_bank *mc_bank, struct domain *d, - uint64_t gstatus) +static int vcpu_fill_mc_msrs(struct vcpu *v, uint64_t mcg_status, + uint64_t mci_status, uint64_t mci_addr, + uint64_t mci_misc) { - struct vcpu *v = d->vcpu[0]; - - if ( mc_bank->mc_domid != DOMID_INVALID ) + if ( v->arch.vmce.mcg_status & MCG_STATUS_MCIP ) { - if ( v->arch.vmce.mcg_status & MCG_STATUS_MCIP ) - { - mce_printk(MCE_QUIET, "MCE: guest has not handled previous" - " vMCE yet!\n"); - return -1; - } + mce_printk(MCE_QUIET, "MCE: %pv: guest has not handled previous" + " vMCE yet!\n", v); + return -EBUSY; + } - spin_lock(&v->arch.vmce.lock); + spin_lock(&v->arch.vmce.lock); - v->arch.vmce.mcg_status = gstatus; - /* - * 1. Skip bank 0 to avoid 'bank 0 quirk' of old processors - * 2. Filter MCi_STATUS MSCOD model specific error code to guest - */ - v->arch.vmce.bank[1].mci_status = mc_bank->mc_status & - MCi_STATUS_MSCOD_MASK; - v->arch.vmce.bank[1].mci_addr = mc_bank->mc_addr; - v->arch.vmce.bank[1].mci_misc = mc_bank->mc_misc; + v->arch.vmce.mcg_status = mcg_status; + /* + * 1. Skip bank 0 to avoid 'bank 0 quirk' of old processors + * 2. Filter MCi_STATUS MSCOD model specific error code to guest + */ + v->arch.vmce.bank[1].mci_status = mci_status & MCi_STATUS_MSCOD_MASK; + v->arch.vmce.bank[1].mci_addr = mci_addr; + v->arch.vmce.bank[1].mci_misc = mci_misc; - spin_unlock(&v->arch.vmce.lock); - } + spin_unlock(&v->arch.vmce.lock); return 0; } +int fill_vmsr_data(struct mcinfo_bank *mc_bank, struct domain *d, + uint64_t gstatus, bool broadcast) +{ + struct vcpu *v = d->vcpu[0]; + int ret, err; + + if ( mc_bank->mc_domid == DOMID_INVALID ) + return -EINVAL; + + /* + * vMCE with the actual error information is injected to vCPU0, + * and, if broadcast is required, we choose to inject less severe + * vMCEs to other vCPUs. Thus guest can always get the severest + * error (i.e. the actual one) on vCPU0. If guest can recover from + * the severest error on vCPU0, the less severe errors on other + * vCPUs will not prevent guest from recovering on those vCPUs. + */ + ret = vcpu_fill_mc_msrs(v, gstatus, mc_bank->mc_status, + mc_bank->mc_addr, mc_bank->mc_misc); + if ( broadcast ) + for_each_vcpu ( d, v ) + { + if ( !v->vcpu_id ) + continue; + err = vcpu_fill_mc_msrs(v, MCG_STATUS_MCIP | MCG_STATUS_RIPV, + 0, 0, 0); + if ( err ) + ret = err; + } + + return ret; +} + /* It's said some ram is setup as mmio_direct for UC cache attribute */ #define P2M_UNMAP_TYPES (p2m_to_mask(p2m_ram_rw) \ | p2m_to_mask(p2m_ram_logdirty) \ diff --git a/xen/arch/x86/cpu/mcheck/vmce.h b/xen/arch/x86/cpu/mcheck/vmce.h index 163ce3c..74f6381 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.h +++ b/xen/arch/x86/cpu/mcheck/vmce.h @@ -17,7 +17,7 @@ int vmce_amd_rdmsr(const struct vcpu *, uint32_t msr, uint64_t *val); int vmce_amd_wrmsr(struct vcpu *, uint32_t msr, uint64_t val); int fill_vmsr_data(struct mcinfo_bank *mc_bank, struct domain *d, - uint64_t gstatus); + uint64_t gstatus, bool broadcast); #define VMCE_INJECT_BROADCAST (-1) int inject_vmce(struct domain *d, int vcpu);