| Message ID | 20170224105256.24668-6-haozhong.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 02/24/2017 05:52 AM, Haozhong Zhang wrote: > On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any > non-zero value would result in #GP. > > This commit writes 0 on AMD CPU as well instead of just clearing MCIP > bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been > handled at this point. > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
>>> On 24.02.17 at 11:52, <haozhong.zhang@intel.com> wrote: > On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any > non-zero value would result in #GP. > > This commit writes 0 on AMD CPU as well instead of just clearing MCIP > bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been > handled at this point. > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 53ca29c..5a7e2ba 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -539,7 +539,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs) gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS); if ((gstatus & MCG_STATUS_MCIP) != 0) { mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step"); - mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP); + mca_wrmsr(MSR_IA32_MCG_STATUS, 0); } mce_barrier_exit(&mce_trap_bar);
On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any non-zero value would result in #GP. This commit writes 0 on AMD CPU as well instead of just clearing MCIP bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been handled at this point. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> --- Cc: Christoph Egger <chegger@amazon.de> Cc: Jan Beulich <jbeulich@suse.com> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Changes: * Write 0 on AMD as well. * Change the patch title to reflect the above change. --- xen/arch/x86/cpu/mcheck/mce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)