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Iglesias" To: Stefano Stabellini Message-ID: <20170302225515.GG23726@toto> References: <20170302083837.GB23726@toto> <20170302085332.GU9606@toto> <06e91a8f-f31d-b016-afdd-c6ef28800b87@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.1.0.1062-22916.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(39840400002)(39450400003)(39410400002)(39850400002)(39860400002)(2980300002)(438002)(24454002)(51914003)(189002)(199003)(51444003)(9170700003)(38730400002)(6246003)(53546006)(39060400002)(110136004)(54356999)(50986999)(23726003)(9786002)(97756001)(76176999)(106466001)(57986006)(63266004)(92566002)(356003)(76506005)(626004)(9686003)(305945005)(33656002)(54906002)(93886004)(4001350100001)(81166006)(2906002)(46406003)(8676002)(77096006)(1076002)(229853002)(189998001)(50466002)(2950100002)(47776003)(33716001)(8936002)(4326008)(6916009)(6666003)(5660300001)(83506001)(18370500001)(107986001); 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB0718 Cc: "Edgar E. Iglesias" , Julien Grall , nd@arm.com, xen-devel@lists.xenproject.org Subject: Re: [Xen-devel] xen/arm and swiotlb-xen: possible data corruption X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Mar 02, 2017 at 02:39:55PM -0800, Stefano Stabellini wrote: > On Thu, 2 Mar 2017, Julien Grall wrote: > > Hi Stefano, > > > > On 02/03/17 19:12, Stefano Stabellini wrote: > > > On Thu, 2 Mar 2017, Julien Grall wrote: > > > > On 02/03/17 08:53, Edgar E. Iglesias wrote: > > > > > On Thu, Mar 02, 2017 at 09:38:37AM +0100, Edgar E. Iglesias wrote: > > > > > > On Wed, Mar 01, 2017 at 05:05:21PM -0800, Stefano Stabellini wrote: > > > Julien, from looking at the two diffs, this is simpler and nicer, but if > > > you look at xen/include/asm-arm/page.h, my patch made > > > clean_dcache_va_range consistent with invalidate_dcache_va_range. For > > > consistency, I would prefer to deal with the two functions the same way. > > > Although it is not a spec requirement, I also think that it is a good > > > idea to issue cache flushes from cacheline aligned addresses, like > > > invalidate_dcache_va_range does and Linux does, to make more obvious > > > what is going on. > > > > invalid_dcache_va_range is split because the cache instruction differs for the > > start and end if unaligned. For them you want to use clean & invalidate rather > > than invalidate. > > > > If you look at the implementation of other cache helpers in Linux (see > > dcache_by_line_op in arch/arm64/include/asm/assembler.h), they will only align > > start & end. > > I don't think so, unless I am reading dcache_by_line_op wrong. > > > > Also, the invalid_dcache_va_range is using modulo which I would rather avoid. > > The modulo in this case will not be optimized by the compiler because > > cacheline_bytes is not a constant. > > That is a good point. What if I replace the modulo op with > > p & (cacheline_bytes - 1) > > in invalidate_dcache_va_range, then add the similar code to > clean_dcache_va_range and clean_and_invalidate_dcache_va_range? Yeah, if there was some kind of generic ALIGN or ROUND_DOWN macro we could do: I think that would achieve the same result as your patch Stefano? Cheers, Edgar > > > > BTW, you would also need to fix clean_and_invalidate_dcache_va_range. > > I'll do that, thanks for the reminder. --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -325,7 +325,9 @@ static inline int clean_dcache_va_range(const void *p, unsigned long size) { const void *end; dsb(sy); /* So the CPU issues all writes to the range */ - for ( end = p + size; p < end; p += cacheline_bytes ) + + p = (void *)ALIGN((uintptr_t)p, cacheline_bytes); + end = (void *)ROUNDUP((uintptr_t)p + size, cacheline_bytes); + for ( ; p < end; p += cacheline_bytes ) asm volatile (__clean_dcache_one(0) : : "r" (p)); dsb(sy); /* So we know the flushes happen before continuing */ /* ARM callers assume that dcache_* functions cannot fail. */