From patchwork Fri Mar 17 06:46:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9629917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ABA9F60245 for ; Fri, 17 Mar 2017 06:49:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A7F628698 for ; Fri, 17 Mar 2017 06:49:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F2912869C; Fri, 17 Mar 2017 06:49:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 756F828698 for ; Fri, 17 Mar 2017 06:49:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1colel-0000R9-7a; Fri, 17 Mar 2017 06:46:35 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1colej-0000Qz-NP for xen-devel@lists.xen.org; Fri, 17 Mar 2017 06:46:33 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id 8E/98-04971-9468BC85; Fri, 17 Mar 2017 06:46:33 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsVywNxEW9e97XS Ewdr1ehZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bTjhlsBTeWM1Zs3D+JvYHxXRNjFyMnh5BA hcT1KfeYQWwJAV6JI8tmsELYARJdBzqA4lxANb2MEt+WfWUBSbAJ6EuseHwQrEhEQFri2ufLY IOYBaolJk6fA2RzcAgLuEv8PREOYrIIqEqc+sMGUsErYCvx+fhiRojx8hIXrp4Cm8gpYCfxsf EWC8Q5thKNDbeZJjDyLmBkWMWoUZxaVJZapGtoqZdUlJmeUZKbmJmja2hgppebWlycmJ6ak5h UrJecn7uJERgODECwg/HHsoBDjJIcTEqivCqCJyKE+JLyUyozEosz4otKc1KLDzHKcHAoSfBy FwDlBItS01Mr0jJzgIEJk5bg4FES4S0FSfMWFyTmFmemQ6ROMSpKifNWgSQEQBIZpXlwbbBou MQoKyXMywh0iBBPQWpRbmYJqvwrRnEORiVhXjaQKTyZeSVw018BLWYCWpz48wjI4pJEhJRUA2 Pt4QrmT2uU1My/T9N3lClm9ExVyajl+qu+27JXla9EsNP8YdJpoZ03qpWlZmtvfMlx7j2zuX/ m+7IzStzMm1M5Pr9+2ZIXoXjnytx5BdqCPSmq4Zw3OCP6zseJ9tvrdgnsF1Sd4FLq+ML3tfO2 tfonBF7JzlpTuHzaxOWqjsvmm/QvzSoJUWIpzkg01GIuKk4EANfNKnKBAgAA X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-11.tower-21.messagelabs.com!1489733189!62664741!1 X-Originating-IP: [192.55.52.43] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 38731 invoked from network); 17 Mar 2017 06:46:31 -0000 Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by server-11.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Mar 2017 06:46:31 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 23:46:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,175,1486454400"; d="scan'208"; a="1109452569" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by orsmga001.jf.intel.com with ESMTP; 16 Mar 2017 23:46:27 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Mar 2017 14:46:03 +0800 Message-Id: <20170317064614.23539-2-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170317064614.23539-1-haozhong.zhang@intel.com> References: <20170317064614.23539-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Jan Beulich , Andrew Cooper Subject: [Xen-devel] [PATCH v2 01/12] xen/mce: switch bool_t/1/0 to bool/true/false X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Haozhong Zhang Acked-by: Jan Beulich --- Cc: Jan Beulich Cc: Andrew Cooper --- xen/arch/x86/acpi/power.c | 2 +- xen/arch/x86/cpu/common.c | 4 +- xen/arch/x86/cpu/mcheck/mcaction.h | 2 +- xen/arch/x86/cpu/mcheck/mce-apei.c | 2 +- xen/arch/x86/cpu/mcheck/mce.c | 32 ++++++++-------- xen/arch/x86/cpu/mcheck/mce.h | 22 +++++------ xen/arch/x86/cpu/mcheck/mce_amd.c | 20 +++++----- xen/arch/x86/cpu/mcheck/mce_amd.h | 4 +- xen/arch/x86/cpu/mcheck/mce_intel.c | 76 ++++++++++++++++++------------------- xen/arch/x86/cpu/mcheck/mctelem.c | 6 +-- xen/arch/x86/cpu/mcheck/mctelem.h | 2 +- xen/arch/x86/cpu/mcheck/x86_mca.h | 4 +- 12 files changed, 88 insertions(+), 88 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 506f54d..1e4e568 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -235,7 +235,7 @@ static int enter_state(u32 state) device_power_up(SAVED_ALL); - mcheck_init(&boot_cpu_data, 0); + mcheck_init(&boot_cpu_data, false); write_cr4(cr4); printk(XENLOG_INFO "Finishing wakeup from ACPI S%d state.\n", state); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 0040fa3..9c44bbd 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -406,9 +406,9 @@ void identify_cpu(struct cpuinfo_x86 *c) for ( i = 0 ; i < NCAPINTS ; i++ ) boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; - mcheck_init(c, 0); + mcheck_init(c, false); } else { - mcheck_init(c, 1); + mcheck_init(c, true); mtrr_bp_init(); } diff --git a/xen/arch/x86/cpu/mcheck/mcaction.h b/xen/arch/x86/cpu/mcheck/mcaction.h index c6044d5..5cbe558 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.h +++ b/xen/arch/x86/cpu/mcheck/mcaction.h @@ -12,7 +12,7 @@ mc_memerr_dhandler(struct mca_binfo *binfo, #define MC_ADDR_PHYSICAL 0 #define MC_ADDR_VIRTUAL 1 -typedef int (*mce_check_addr_t)(uint64_t status, uint64_t misc, int addr_type); +typedef bool (*mce_check_addr_t)(uint64_t status, uint64_t misc, int addr_type); extern void mce_register_addrcheck(mce_check_addr_t); extern mce_check_addr_t mc_check_addr; diff --git a/xen/arch/x86/cpu/mcheck/mce-apei.c b/xen/arch/x86/cpu/mcheck/mce-apei.c index 3933c19..53b6735 100644 --- a/xen/arch/x86/cpu/mcheck/mce-apei.c +++ b/xen/arch/x86/cpu/mcheck/mce-apei.c @@ -116,7 +116,7 @@ ssize_t apei_read_mce(struct mce *m, u64 *record_id) } /* Check whether there is record in ERST */ -bool_t apei_check_mce(void) +bool apei_check_mce(void) { return erst_get_record_count() > 0; } diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index cd4f0ee..df2e3a4 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -30,10 +30,10 @@ #include "util.h" #include "vmce.h" -bool_t __read_mostly opt_mce = 1; +bool __read_mostly opt_mce = true; boolean_param("mce", opt_mce); -bool_t __read_mostly mce_broadcast = 0; -bool_t is_mc_panic; +bool __read_mostly mce_broadcast; +bool is_mc_panic; unsigned int __read_mostly nr_mce_banks; unsigned int __read_mostly firstbank; uint8_t __read_mostly cmci_apic_vector; @@ -285,7 +285,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask, uint64_t gstatus, status; struct mcinfo_global *mig = NULL; /* on stack */ mctelem_cookie_t mctc = NULL; - bool_t uc = 0, pcc = 0, recover = 1, need_clear = 1; + bool uc = false, pcc = false, recover = true, need_clear = true; uint32_t mc_flags = 0; struct mc_info *mci = NULL; mctelem_class_t which = MC_URGENT; /* XXXgcc */ @@ -356,14 +356,14 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask, /* flag for uncorrected errors */ if (!uc && ((status & MCi_STATUS_UC) != 0)) - uc = 1; + uc = true; /* flag processor context corrupt */ if (!pcc && ((status & MCi_STATUS_PCC) != 0)) - pcc = 1; + pcc = true; if (recover && uc) - /* uc = 1, recover = 1, we need not panic. + /* uc = true, recover = true, we need not panic. */ recover = mc_recoverable_scan(status); @@ -372,7 +372,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask, if (mc_callback_bank_extended) mc_callback_bank_extended(mci, i, status); - /* By default, need_clear = 1 */ + /* By default, need_clear = true */ if (who != MCA_MCE_SCAN && need_clear) /* Clear bank */ mcabank_clear(i); @@ -554,7 +554,7 @@ void mcheck_mca_clearbanks(struct mca_banks *bankmask) } /*check the existence of Machine Check*/ -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -719,7 +719,7 @@ static struct notifier_block cpu_nfb = { }; /* This has to be run for each processor */ -void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp) +void mcheck_init(struct cpuinfo_x86 *c, bool bsp) { enum mcheck_type inited = mcheck_none; @@ -1059,15 +1059,15 @@ static void intpose_add(unsigned int cpu_nr, uint64_t msr, uint64_t val) printk("intpose_add: interpose array full - request dropped\n"); } -bool_t intpose_inval(unsigned int cpu_nr, uint64_t msr) +bool intpose_inval(unsigned int cpu_nr, uint64_t msr) { struct intpose_ent *ent = intpose_lookup(cpu_nr, msr, NULL); if ( !ent ) - return 0; + return false; ent->cpu_nr = -1; - return 1; + return true; } #define IS_MCA_BANKREG(r) \ @@ -1075,7 +1075,7 @@ bool_t intpose_inval(unsigned int cpu_nr, uint64_t msr) (r) <= MSR_IA32_MCx_MISC(nr_mce_banks - 1) && \ ((r) - MSR_IA32_MC0_CTL) % 4 != 0) /* excludes MCi_CTL */ -static int x86_mc_msrinject_verify(struct xen_mc_msrinject *mci) +static bool x86_mc_msrinject_verify(struct xen_mc_msrinject *mci) { struct cpuinfo_x86 *c; int i, errs = 0; @@ -1569,7 +1569,7 @@ static void mc_panic_dump(void) void mc_panic(char *s) { - is_mc_panic = 1; + is_mc_panic = true; console_force_unlock(); printk("Fatal machine check: %s\n", s); @@ -1669,7 +1669,7 @@ static int mce_delayed_action(mctelem_cookie_t mctc) { case MCER_RESET: dprintk(XENLOG_ERR, "MCE delayed action failed\n"); - is_mc_panic = 1; + is_mc_panic = true; x86_mcinfo_dump(mctelem_dataptr(mctc)); panic("MCE: Software recovery failed for the UCR"); break; diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 4129a99..7611789 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -41,7 +41,7 @@ extern uint8_t cmci_apic_vector; /* Init functions */ enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c); -enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool bsp); void amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c); @@ -50,7 +50,7 @@ extern unsigned int firstbank; struct mcinfo_extended *intel_get_extended_msrs( struct mcinfo_global *mig, struct mc_info *mi); -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); unsigned int mce_firstbank(struct cpuinfo_x86 *c); /* Helper functions used for collecting error telemetry */ void noreturn mc_panic(char *s); @@ -66,13 +66,13 @@ extern void x86_mce_vector_register(x86_mce_vector_t); extern void mcheck_cmn_handler(const struct cpu_user_regs *regs); /* Register a handler for judging whether mce is recoverable. */ -typedef int (*mce_recoverable_t)(uint64_t status); +typedef bool (*mce_recoverable_t)(uint64_t status); extern void mce_recoverable_register(mce_recoverable_t); /* Read an MSR, checking for an interposed value first */ extern struct intpose_ent *intpose_lookup(unsigned int, uint64_t, uint64_t *); -extern bool_t intpose_inval(unsigned int, uint64_t); +extern bool intpose_inval(unsigned int, uint64_t); static inline uint64_t mca_rdmsr(unsigned int msr) { @@ -107,18 +107,18 @@ struct mca_summary { uint32_t errcnt; /* number of banks with valid errors */ int ripv; /* meaningful on #MC */ int eipv; /* meaningful on #MC */ - bool_t uc; /* UC flag */ - bool_t pcc; /* PCC flag */ - bool_t recoverable; /* software error recoverable flag */ + bool uc; /* UC flag */ + bool pcc; /* PCC flag */ + bool recoverable; /* software error recoverable flag */ }; DECLARE_PER_CPU(struct mca_banks *, poll_bankmask); DECLARE_PER_CPU(struct mca_banks *, no_cmci_banks); DECLARE_PER_CPU(struct mca_banks *, mce_clear_banks); -extern bool_t cmci_support; -extern bool_t is_mc_panic; -extern bool_t mce_broadcast; +extern bool cmci_support; +extern bool is_mc_panic; +extern bool mce_broadcast; extern void mcheck_mca_clearbanks(struct mca_banks *); extern mctelem_cookie_t mcheck_mca_logout(enum mca_source, struct mca_banks *, @@ -131,7 +131,7 @@ extern mctelem_cookie_t mcheck_mca_logout(enum mca_source, struct mca_banks *, */ /* Register a handler for judging whether the bank need to be cleared */ -typedef int (*mce_need_clearbank_t)(enum mca_source who, u64 status); +typedef bool (*mce_need_clearbank_t)(enum mca_source who, u64 status); extern void mce_need_clearbank_register(mce_need_clearbank_t); /* Register a callback to collect additional information (typically non- diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c index fe51be9..c580a91 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -103,15 +103,15 @@ mc_ec2type(uint16_t errorcode) return 0; } -int +bool mc_amd_recoverable_scan(uint64_t status) { - int ret = 0; + bool ret = false; enum mc_ec_type ectype; uint16_t errorcode; if ( !(status & MCi_STATUS_UC) ) - return 1; + return true; errorcode = status & (MCi_STATUS_MCA | MCi_STATUS_MSEC); ectype = mc_ec2type(errorcode); @@ -122,7 +122,7 @@ mc_amd_recoverable_scan(uint64_t status) /* should run cpu offline action */ break; case MC_EC_MEM_TYPE: /* value in addr MSR is physical */ - ret = 1; /* run memory page offline action */ + ret = true; /* run memory page offline action */ break; case MC_EC_TLB_TYPE: /* value in addr MSR is virtual */ /* should run tlb flush action and retry */ @@ -132,7 +132,7 @@ mc_amd_recoverable_scan(uint64_t status) return ret; } -int +bool mc_amd_addrcheck(uint64_t status, uint64_t misc, int addrtype) { enum mc_ec_type ectype; @@ -152,7 +152,7 @@ mc_amd_addrcheck(uint64_t status, uint64_t misc, int addrtype) /* unreached */ BUG(); - return 0; + return false; } /* MC quirks */ @@ -238,19 +238,19 @@ amd_f10_handler(struct mc_info *mi, uint16_t bank, uint64_t status) return mc_ext; } -static int amd_need_clearbank_scan(enum mca_source who, uint64_t status) +static bool amd_need_clearbank_scan(enum mca_source who, uint64_t status) { if ( who != MCA_MCE_SCAN ) - return 1; + return true; /* * For fatal error, it shouldn't be cleared so that sticky bank * have a chance to be handled after reboot by polling. */ if ( (status & MCi_STATUS_UC) && (status & MCi_STATUS_PCC) ) - return 0; + return false; - return 1; + return true; } /* AMD specific MCA MSR */ diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.h b/xen/arch/x86/cpu/mcheck/mce_amd.h index de5fc48..67c4545 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.h +++ b/xen/arch/x86/cpu/mcheck/mce_amd.h @@ -1,7 +1,7 @@ #ifndef _MCHECK_AMD_H #define _MCHECK_AMD_H -int mc_amd_recoverable_scan(uint64_t status); -int mc_amd_addrcheck(uint64_t status, uint64_t misc, int addrtype); +bool mc_amd_recoverable_scan(uint64_t status); +bool mc_amd_addrcheck(uint64_t status, uint64_t misc, int addrtype); #endif diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 189c1ed..b0d8280 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -22,9 +22,9 @@ #include "mcaction.h" static DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_banks_owned); -bool_t __read_mostly cmci_support = 0; -static bool_t __read_mostly ser_support = 0; -static bool_t __read_mostly mce_force_broadcast; +bool __read_mostly cmci_support; +static bool __read_mostly ser_support; +static bool __read_mostly mce_force_broadcast; boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; @@ -81,13 +81,13 @@ static void intel_thermal_interrupt(struct cpu_user_regs *regs) } /* Thermal monitoring depends on APIC, ACPI and clock modulation */ -static int intel_thermal_supported(struct cpuinfo_x86 *c) +static bool intel_thermal_supported(struct cpuinfo_x86 *c) { if (!cpu_has_apic) - return 0; + return false; if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_TM1)) - return 0; - return 1; + return false; + return true; } static u32 __read_mostly lvtthmr_init; @@ -268,12 +268,12 @@ static void intel_memerr_dhandler( mc_memerr_dhandler(binfo, result, regs); } -static int intel_srar_check(uint64_t status) +static bool intel_srar_check(uint64_t status) { return ( intel_check_mce_type(status) == intel_mce_ucr_srar ); } -static int intel_checkaddr(uint64_t status, uint64_t misc, int addrtype) +static bool intel_checkaddr(uint64_t status, uint64_t misc, int addrtype) { if (!(status & MCi_STATUS_ADDRV) || !(status & MCi_STATUS_MISCV) || @@ -307,7 +307,7 @@ static void intel_srar_dhandler( } } -static int intel_srao_check(uint64_t status) +static bool intel_srao_check(uint64_t status) { return ( intel_check_mce_type(status) == intel_mce_ucr_srao ); } @@ -336,7 +336,7 @@ static void intel_srao_dhandler( } } -static int intel_default_check(uint64_t status) +static bool intel_default_check(uint64_t status) { return 1; } @@ -398,51 +398,51 @@ static const struct mca_error_handler intel_mce_uhandlers[] = { * 3) ser_support = 1, SRAO, UC = 1, S = 1, AR = 0, [EN = 1] */ -static int intel_need_clearbank_scan(enum mca_source who, u64 status) +static bool intel_need_clearbank_scan(enum mca_source who, u64 status) { if ( who == MCA_CMCI_HANDLER) { /* CMCI need clear bank */ if ( !(status & MCi_STATUS_UC) ) - return 1; + return true; /* Spurious need clear bank */ else if ( ser_support && !(status & MCi_STATUS_OVER) && !(status & MCi_STATUS_EN) ) - return 1; + return true; /* UCNA OVER = 0 need clear bank */ else if ( ser_support && !(status & MCi_STATUS_OVER) && !(status & MCi_STATUS_PCC) && !(status & MCi_STATUS_S) && !(status & MCi_STATUS_AR)) - return 1; + return true; /* Only Log, no clear */ - else return 0; + else return false; } else if ( who == MCA_MCE_SCAN) { if ( !ser_support ) - return 0; + return false; /* * For fatal error, it shouldn't be cleared so that sticky bank * have chance to be handled after reboot by polling */ if ( (status & MCi_STATUS_UC) && (status & MCi_STATUS_PCC) ) - return 0; + return false; /* Spurious need clear bank */ else if ( !(status & MCi_STATUS_OVER) && (status & MCi_STATUS_UC) && !(status & MCi_STATUS_EN)) - return 1; + return true; /* SRAR OVER=0 clear bank. OVER = 1 have caused reset */ else if ( (status & MCi_STATUS_UC) && (status & MCi_STATUS_S) && (status & MCi_STATUS_AR ) && !(status & MCi_STATUS_OVER) ) - return 1; + return true; /* SRAO need clear bank */ else if ( !(status & MCi_STATUS_AR) && (status & MCi_STATUS_S) && (status & MCi_STATUS_UC)) - return 1; + return true; else - return 0; + return false; } - return 1; + return true; } /* MCE continues/is recoverable when @@ -452,30 +452,30 @@ static int intel_need_clearbank_scan(enum mca_source who, u64 status) * 4) SRAO ser_support = 1, PCC = 0, S = 1, AR = 0, EN = 1 [UC = 1] * 5) UCNA ser_support = 1, OVER = 0, EN = 1, PCC = 0, S = 0, AR = 0, [UC = 1] */ -static int intel_recoverable_scan(uint64_t status) +static bool intel_recoverable_scan(uint64_t status) { if ( !(status & MCi_STATUS_UC ) ) - return 1; + return true; else if ( ser_support && !(status & MCi_STATUS_EN) && !(status & MCi_STATUS_OVER) ) - return 1; + return true; /* SRAR error */ else if ( ser_support && !(status & MCi_STATUS_OVER) && !(status & MCi_STATUS_PCC) && (status & MCi_STATUS_S) && (status & MCi_STATUS_AR) && (status & MCi_STATUS_EN) ) - return 1; + return true; /* SRAO error */ else if (ser_support && !(status & MCi_STATUS_PCC) && (status & MCi_STATUS_S) && !(status & MCi_STATUS_AR) && (status & MCi_STATUS_EN)) - return 1; + return true; /* UCNA error */ else if (ser_support && !(status & MCi_STATUS_OVER) && (status & MCi_STATUS_EN) && !(status & MCi_STATUS_PCC) && !(status & MCi_STATUS_S) && !(status & MCi_STATUS_AR)) - return 1; - return 0; + return true; + return false; } /* CMCI */ @@ -686,10 +686,10 @@ static void intel_init_cmci(struct cpuinfo_x86 *c) /* MCA */ -static int mce_is_broadcast(struct cpuinfo_x86 *c) +static bool mce_is_broadcast(struct cpuinfo_x86 *c) { if (mce_force_broadcast) - return 1; + return true; /* According to Intel SDM Dec, 2009, 15.10.4.1, For processors with * DisplayFamily_DisplayModel encoding of 06H_EH and above, @@ -697,14 +697,14 @@ static int mce_is_broadcast(struct cpuinfo_x86 *c) */ if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 6 && c->x86_model >= 0xe) - return 1; - return 0; + return true; + return false; } /* Check and init MCA */ static void intel_init_mca(struct cpuinfo_x86 *c) { - bool_t broadcast, cmci = 0, ser = 0; + bool broadcast, cmci = false, ser = false; int ext_num = 0, first; uint64_t msr_content; @@ -713,11 +713,11 @@ static void intel_init_mca(struct cpuinfo_x86 *c) rdmsrl(MSR_IA32_MCG_CAP, msr_content); if ((msr_content & MCG_CMCI_P) && cpu_has_apic) - cmci = 1; + cmci = true; /* Support Software Error Recovery */ if (msr_content & MCG_SER_P) - ser = 1; + ser = true; if (msr_content & MCG_EXT_P) ext_num = (msr_content >> MCG_EXT_CNT) & 0xff; @@ -856,7 +856,7 @@ static struct notifier_block cpu_nfb = { }; /* p4/p6 family have similar MCA initialization process */ -enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp) +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool bsp) { if ( bsp ) { diff --git a/xen/arch/x86/cpu/mcheck/mctelem.c b/xen/arch/x86/cpu/mcheck/mctelem.c index f26f13d..96048eb 100644 --- a/xen/arch/x86/cpu/mcheck/mctelem.c +++ b/xen/arch/x86/cpu/mcheck/mctelem.c @@ -189,11 +189,11 @@ void mctelem_process_deferred(unsigned int cpu, } } -int mctelem_has_deferred(unsigned int cpu) +bool mctelem_has_deferred(unsigned int cpu) { if (per_cpu(mctctl.pending, cpu) != NULL) - return 1; - return 0; + return true; + return false; } /* Free an entry to its native free list; the entry must not be linked on diff --git a/xen/arch/x86/cpu/mcheck/mctelem.h b/xen/arch/x86/cpu/mcheck/mctelem.h index 4947b57..9fcde4f 100644 --- a/xen/arch/x86/cpu/mcheck/mctelem.h +++ b/xen/arch/x86/cpu/mcheck/mctelem.h @@ -70,6 +70,6 @@ extern void mctelem_ack(mctelem_class_t, mctelem_cookie_t); extern void mctelem_defer(mctelem_cookie_t); extern void mctelem_process_deferred(unsigned int, int (*)(mctelem_cookie_t)); -int mctelem_has_deferred(unsigned int); +bool mctelem_has_deferred(unsigned int); #endif diff --git a/xen/arch/x86/cpu/mcheck/x86_mca.h b/xen/arch/x86/cpu/mcheck/x86_mca.h index e25d619..34d1921 100644 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h @@ -147,12 +147,12 @@ struct mca_error_handler * a seperate function to decode the corresponding actions * for the particular mca error later. */ - int (*owned_error)(uint64_t status); + bool (*owned_error)(uint64_t status); void (*recovery_handler)(struct mca_binfo *binfo, enum mce_result *result, const struct cpu_user_regs *regs); }; /* Global variables */ -extern bool_t opt_mce; +extern bool opt_mce; #endif /* X86_MCA_H */